A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique

Abstract

This paper presents a linearity-enhanced 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a high-speed and low-noise comparator. A p-well floating technique for linearity improvement of sampling switch is proposed. The total parasitic capacitance of the sampling switch is depressed compared to conventional structures. Also, the variation of parasitic capacitance is reduced. Furthermore, a substrate voltage boosting technique is proposed to depress the noise of comparator at a high conversion rate. In addition, an improved parallel SAR logic is exhibited to increase the speed of SAR feedback loop and enhance the settling of digital-to-analog converter (DAC). Last, an adaptive sampling technique is utilized to increase the sampling time of SAR ADC. The proposed SAR ADC is fabricated in the 65-nm CMOS process, consuming 2 mW at a 1.2-V power supply. It achieves a signal-to-noise distortion ratio (SNDR) >55.6 dB and spurious-free dynamic range (SFDR) >69 dB at 160 MS/s. The ADC core occupies an active area of 0.023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the corresponding figure-of-merit (FoM) is 25.4 fJ/conversion-step at Nyquist input.