Abstract
Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.
Highlights
Demands for energy-efficient applications, such as the Internet of Things (IoT), batteryoperated sensors, and wearable electronics, are continuously increasing
We propose a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) featuring a passive gain multiplication technique and successfully verify the approach using a chip fabricated in a 0.18 μm CMOS
We embed the charge pump in the noise shaping filter to boost the gain without static power consumption, which effectively deals with the residue voltage attenuation
Summary
Demands for energy-efficient applications, such as the Internet of Things (IoT), batteryoperated sensors, and wearable electronics, are continuously increasing. The previous work on the SAR ADC realizes the noise shaping filter using opamp and achieves a 10-bit effective number of bits (ENOB) using 8-bit CDAC [7]. To handle the small residue, the differential input pair for the residue is sized larger than the one other receiving the DAC output This approach provides the advantage of the increased gain for processing the residue; the kickback noise of the comparator is proportionally increased with the size of the input pair (or the capacitance). The previous approaches suffer from the tradeoff between gain, kickback, and input-referred noise These results indicate that the noise shaping technique suitable for simple and power-efficient SAR ADC has not been fully investigated. We embed a charge pump in the filter for passive gain multiplication to deal with the residue attenuation in the previous passive noise shaping This approach uses only capacitors and switches in the FIR and IIR filters. 79.1 dB with a figure-of-merit (FoM) of 11.8 fJ/conversion-step
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