A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS

Abstract

This paper presents a wideband 12 bit 8 GS/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC), featuring a sub-2 radix capacitive digital-to-analog converter (C-DAC) architecture using a 28 nm CMOS technology. A total of 18 500 MHz SAR-ADCs are interleaved to achieve the targeted 8 GS/s sample rate, while incorporating a sub-2 radix architecture with an overrange of 10%. The use of 18 interleaved ADCs enable an extended channel randomization approach, reducing mismatch related interleaving spurs. An additional reference ADC operating in parallel to the main ADC enables advanced digital calibration to correct for static and time-interleaved mismatch effects. The wideband sampling front-end features two subsequent push-pull buffer stages to achieve a high T & H bandwidth and high sampling linearity, while improving kickback related settling limitations. Due to the absence of a dedicated front-end T & H, the input signal is sampled by the individual SAR. The ADC achieves a signal to noise and distortion ratio (SNDR) of 56.8 dB and a spurious free dynamic range (SFDR) of 73.5 dBc applying a single full scale sine wave tone at Nyquist frequency of 4 GHz.