Capacitor Size Research Articles

Comprehensive Analysis and Evaluation of DC-Link Voltage and Current Ripples in Symmetric and Asymmetric Two-Level Six-Phase Voltage Source Inverters

Multiphase drives (MPD) in general and six-phase in particular have been gaining popularity in many industries, which calls for a proper multiphase inverter (MPI) design. For voltage source inverter (VSI)-fed drives, the knowledge of voltage and current stresses on the dc-link are imperative for input capacitor sizing. To this end, the voltage and current stresses on the dc-link capacitor in two-level six-phase VSIs are examined thoroughly in this article for two configurations of load/winding spatial distribution: symmetric and asymmetric. First, the harmonic spectrum of the input dc current of each inverter is analyzed in detail by benchmarking them against the conventional three-phase VSI, to precisely establish the dc-capacitor requirement reduction in six-phase counterparts. Second, analytical formulae for the dc-link capacitor voltage ripples are derived for both configurations. Third, simple formulae for dc-capacitor sizing for six-phase VSIs with different load configurations are provided. The accuracy of the derived formulae is verified by simulation and experimental testing at various power factors and modulation depth. It is found that six-phase VSI supplying symmetric and asymmetric loads reaps 10% and 7% lower dc-link current ripples, respectively. Hence, six-phase symmetric loads yield the smallest capacitor size.

Dual Boost Five-Level Switched-Capacitor Inverter With Common Ground

This brief presents a five-level common ground type (5L-CGT) inverter topology with double voltage boosting. This topology uses only eight switches, two capacitors that can be charged equal to the input source. The advantageous feature of this topology is the CGT configuration between the input source and output load, which ensures minimal common-mode voltage and leakage current. A detailed analysis is done to select and size capacitors, along with quasi-soft charging to minimize the charging current ripples across the capacitors. The performance of the proposed 5L-CGT inverter is tested for inductive load, varying the modulation index/load/input voltage under experimental test conditions. A detailed comparison is done with the existing state-of-art that shows the merits of the proposed topology in terms of equal voltage stress across the capacitor with voltage boost. The power loss analysis for the inverter is carried out using PLECS with efficiency to be 97.20%, and the experimental efficiency is found to be 96.54% for the 900W inverter prototype.

Optimization-Based Methodology to Design the MMC's Sub-Module Capacitors

This paper proposes an optimization-based size reduction methodology for Modular Multilevel Converters (MMC), focusing on minimizing the converter's sub-module capacitor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_{SM}$</tex-math></inline-formula> . The analysis is performed considering both the converter's current and voltage limitations and the Transmission System Operator (TSO) Fault Ride Through (FRT) requirements. By means of a steady-state analysis, the time-domain expressions of the converter's arms energies are obtained and their behavior throughout the MMC's operating range is shown. Based on these expressions, the optimization-based problem to reduce the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_{SM}$</tex-math></inline-formula> size is developed and its constraints are imposed to ensure that the converter's voltage and current levels are within its design limitations. The suggested method is compared with different approaches for distinct active and reactive power set-points, where it is shown that the SM capacitor size can be reduced up to 24% in comparison with the method with worst performance and up to 7% regarding the best method used for comparison purposes. Furthermore, time-domain simulations of the MMC considering several AC voltage sags are performed in order to demonstrate that the dynamics of the SM capacitor and the arm applied voltages are within acceptable margins during the different operations.

Batteryless NB-IoT prototype for bidirectional communication powered by ambient light

IoT use-cases aim to provide high-quality services where IoT infrastructures are always linked with the Internet. They require large scale deployment of small devices acting as sensors and actuators in different places. These devices need to be energy efficient and run sustainably. The maintenance of such large scale devices is difficult if they are powered by batteries that need to be replaced after some time. Moreover, disposing of these batteries also pollutes the soil and contaminates groundwater. Narrowband IoT (NB-IoT) is one of the long-range technologies that supports connectivity even in deep indoor closed areas such as underground parking lots, elevators, and tunnels. Therefore, in this article, the suitability of an NB-IoT device or User Equipment (UE) to be powered without any batteries to enable a long-term sustainable maintenance-free IoT network is demonstrated. We develop a prototype using a small photovoltaic solar panel for indoor light harvesting using sunlight or an artificial light bulb to power the NB-IoT UE. Due to the unpredictability of energy harvesting, the batteryless UE can experience frequent switches between the ON and OFF states. Therefore, we evaluate the performance of the solution where the UE communicates either uni- (uplink only) or bi-directionally (uplink and downlink) for different capacitor sizes at different artificial light intensities. We also evaluate the solution under dynamic harvesting power using natural light during daytime. The experimental results conclude that the batteryless NB-IoT UE supports a transmission interval of 60 s without experiencing any restarts when harvesting 6 mW or more, which can be harvested by placing a 6 W artificial light bulb at a distance of 60 cm or less.

Analytical evaluation of single‐input dual‐output based integrated luo‐buck converter for BLDC motor

AbstractA single‐input dual‐output (SIDO) converter is proposed in the research article for usage in electric vehicle (EV) applications. The main objectives of the proposed integrated Luo‐Buck converter (ILBC) based BLDC drive system are to develop a multi‐purpose converter with low complexity and high efficiency, as well as to reach the rated speed of BLDC‐based vehicles. The multi‐output converter is generally employed in EV applications because of the primary load and extra auxiliary loads like sensors, power steering, headlights, and so on. The proposed system achieves both of the aforementioned objectives. As there are just two switches, fewer gate driver circuits are required, which indirectly lowers the complexity of the circuit. Since they do not require large duty cycles, ILBC switches experience less voltage and current stress. The switches can only be used at duty cycles of 60% and 30%. For design purposes, output filter capacitor sizes are likewise maintained to a minimum. The 1.2 kW BLDC is powered by the ILBC, which has a maximum efficiency of 96.16%, in order to validate the suggested system using the hardware prototype model. The rated speed can be attained with the least amount of timing. Additionally, the suggested approach lessens voltage and torque ripple.

A New Generalised Symmetrical/Asymmetrical Boost Integrated Multilevel Inverter with Reduced Components for PV/UPS Applications

ABSTRACT This paper proposes a new generalised boost integrated multilevel inverter (MLI) with reduced components. The proposed MLI is developed by using a modified boost integrated switched capacitor unit, which provides four-level output from each cell. The operation of the proposed MLI for symmetrical 17-level operation with sinusoidal pulse width modulation & nearest level control and asymmetrical 31-level operation with NLC is explained and validated experimentally. The experimental results of static and dynamic load conditions are analysed and discussed in detail. In addition, the proposed topology is compared with recent boost MLI topologies in terms of component count, device stress, efficiency, capacitor size and cost. From the comparative study, it is evident that the proposed MLI provides features such as reduced component count, capacitors size, overall cost and improved voltage gain.

Loss analysis of perspective multiphase converter topology suitable for the automotive traction inverter

The paper deals with the power losses of semiconductor devices of alternative multiphase topology for traction inverters in the automotive industry. Multiphase traction inverters are getting increasingly more attention due to features that make them superior to conventional three-phase topology used nowadays in the automotive industry. Based on key features of multiphase traction inverter topologies, which are enhanced per-phase power management, fault-tolerance capabilities, and decreased size of DC-Link capacitors, are getting the attention of automotive constructors and their suppliers. Power loss calculation is one of the most important aspects of evaluating the estimated efficiency of the proposed topology of the traction inverter. Power Losses are calculated by using the software PLECS.

Hybrid Modular Multilevel Converters for High-AC/Low-DC Medium-Voltage Applications

With ever-increasing power-density requirements, technologies such as energy storage systems and electric-vehicles can benefit greatly from interfacing medium-voltage (MV)-AC grid like 13.8kV or 30kV using high-AC/low-DC voltage converter. Using modular high-AC/low-DC voltage converter can help increase power-density and efficiency, while reducing total conversion steps and providing flexibility. Full-bridge modular multilevel converters (FB-MMC) and solid-state transformers are existing solutions for such operations, but suffer from limitations of high semiconductor requirements, large submodule capacitors and/or many high-frequency transformers. Three new hybrid-MMC (HMMC) topologies are proposed in this paper as alternative solutions for such high-AC/low-DC voltage operations. Each of the three developed HMMCs utilizes a unique combination of low-frequency high-voltage switches and fast-switching low-voltage switch based submodules to generate multilevel-AC voltage. HMMCs are compared extensively to state-of-the-art FB-MMC and are shown to have semiconductor savings of over 27%, 38% lower submodule capacitor size, and 53% lower losses for 13.8-kV-AC/6-kV-DC operation. Due to these benefits like higher efficiency, significantly smaller submodule capacitance requirements, and fewer semiconductors, HMMCs can be an excellent option for high-AC/low-DC applications. Practical considerations like snubber and DC split-capacitor requirement are also elaborated for developing and commercializing HMMCs. Comparison results are verified using a 17.5 kW three-phase MV laboratory prototype.

A methodological approach to design a coil for localised high-frequency induction heating of flat plate

High-frequency induction heating (HFIH) is a quick heating technology, mostly used for localised surface treatment. The HFIH process has a portable RLC tank circuit consisting of a fixed size capacitor bank, load-matching transformer and a small size inductor coil. However, the work feasibility of small size inductor coil involves complexity in matching the resonant frequency between the RLC tank circuit and the high-frequency induction power source. Because the resonant frequency of the RLC tank circuit depends on the shape, size and configuration of the considered inductor coil. To address the issue, a numerical model-based approach is proposed herein to do the frequency matching for any coil configurations. Three different coil configurations such as co-direction, single-direction and opposite-direction current coils are considered in the simulation study to optimise their geometry and estimation of resonant frequencies. Based on the derived resonant frequency of the inductor coils, another coupled electromagnetic-thermal model is developed to get the thermal characteristics for a planar heating process of an 8 mm thick mild steel plate. After finding the optimal geometry of all coil configurations, the coils are fabricated and used in experimentation to verify the results of numerical models. It is found that the coil geometry has a significant effect on the resonant frequency and the heating characteristics. In addition, the current work emphasises a systematic approach to address the temperature non-uniformity that arises at the inlet and outlet positions of the workpiece in movable induction heating.

Optimum Power Flow with Respect to the Capacitor Location and Size in Distribution Network

In the past few decades, there has been increasing recognition of the importance of optimum power flow (OPF) studies in the context of economic analyses of power systems. There is a need for power system development to maximize efficiency by emphasizing cost and power losses for smart grids to operate effectively in the current situation. This study aims to develop an optimal capacitor bank allocation schedule that minimizes power losses in the distribution networks under equality constraints. This will be achieved by integrating the loss factor and voltage stability into a new approach to determine where the capacitor banks should be located. It aims to reduce the operating costs of power systems and maximize efficiency by applying an optimization model for economic dispatch, which considers distributed power generation and demand response. The NSGA-II optimization algorithm was used in this study to determine the optimal size and location of the capacitor bank. A NSGA-II solves this problem by minimizing cost and power losses while determining the best operating strategy. We used an IEEE 26-bus distribution system to test the proposed method with every possible generation change. Comparing the power flow analysis with/without capacitor optimization showed that the operation optimization model of OPF with NSGA-II can reduce operation costs and improve the power system.

Compensation of Distributed Generations Outage Using Controlled Switched Capacitors

Researchers recently came up with innovative ways to generate enough electricity to meet the rising demand through establishing an electricity distribution system and enhancing power quality on the customer side. One of these innovative ways is the installation of distributed generation (DG). DG is widely used in modern networks due to its great benefits of improving the voltage profile and the system’s power quality. Additionally, DGs are ideally placed near the end user in distribution systems to improve the system’s performance while minimizing power losses and enhancing voltage profile in the grid. DG recently grew in importance, and its penetration increased in most distribution systems. Due to the spreading of DG in the power system, the dynamic performance of the system is affected. This paper studies the system’s performance and behavior under condition of DG outage from the system. The model of DGs in this study assumes two cases of the power provided to the network; the first case considered DG units injecting active power only to the grid (unity power factor). In the second case, DG injects both active and reactive power to the system. After that, outage of DG units is fixed by injecting a reactive power source using a capacitor with a controlled switch to compensate the outage of DGs from the distribution system and to reduce the outage’s negative effect on the network. The sizing of capacitors is optimized using a harmony search algorithm (HSA) in the same location of the DG units.

A High Voltage Gain Capable MMC for Offshore Wind Farms: Frequency Component Analysis and Minimization of Capacitor Voltage Ripple

Modular multilevel converter (MMC) and HVdc technology together provide an indispensable solution to integrate offshore wind farms with onshore ac grid. However, the bulky size of MMC and voltage boosting transformers (VBTs) pose a big challenge to keep the footprint and cost of the onshore-platform low. With this background, a full-bridge submodule (SM) modified MMC and a suitably modified switching function are proposed, which utilize the negative SM voltage to achieve ac side voltage boosting. How much negative SM voltages are to be applied across the arms is determined by the group submodule ratio (GSR) parameter, introduced in the switching function. The acquired boosting ability not only shrinks the voltage boosting requirement of VBTs but also reduces the semiconductor switches (upto 10%) and/or the SM count (8%–30%). Analytical solutions derived for the SM capacitor sizing are also presented. The analysis is further utilized to obtain a novel circulating current injection scheme (CCIS), which utilizes phasor analysis to obtain the values of circulating current control parameters. The CCIS suppresses SM capacitor voltage ripple, especially fundamental, and reduces the capacitance requirement by 10%–15% for a wide range of GSR. Representative simulation results are showcased, and the theoretical claims are validated by hardware experiment.

Dual techniques of load shedding and capacitor placement considering load models for optimal distribution system

&lt;span lang="EN-US"&gt;Voltage stability represents one of the main issues in electrical power system. Under voltage load shedding (UVLS) has long been regarded as one of the most successful techniques to prevent the voltage collapse. However, the ordinary load shedding schemes do not consider the different load models and decreasing in the ‎economic cost that resulted from load disconnection, so the dual techniques of load shedding with reactive compensation are needed. Usually loads being modeled as constant power, while in fact of load flow the various load models are utilized. An investigation of optimal dual load shedding with reactive compensation for distribution system based on direct backward forward sweep method (DBFSM) load flow along with a comparison among the other load models are presented in this paper. The teaching learning-based optimization (TLBO) algorithm is executed in order to reduce power losses and enhance the voltage profile. This algorithm is tested and applied to IEEE-16 bus distribution test system to find the optimal superior capacitor size and placement while minimizing load shading for the network. Five different load shedding sequences are considered and the optimization performance of load models demonstrated the comparison through MATLAB program.&lt;/span&gt;

Large Signal Analysis on Variations of the Hybridized Dickson Switched-Capacitor Converter

Dickson-type dc–dc converters have gained renewed interest in recent years due to their best-in-class volt-amp switch utilization. In addition, “hybrid” switched-capacitor (HSC) structures increase passive component utilization while avoiding the slow-switching limit (SSL), and yet, most HSC work to date has done little to assess large signal voltage ripple behavior and subsequent passive utilization limits. This work contributes a comprehensive review of contemporary Dickson-type HSC converters before introducing eight fundamental reduced HSC Dickson structures, including three that are proposed here. Analysis allowing characterization of large signal operating points, capacitor sizing regimes, switching schemes, and maximum allowable power throughput is introduced. The analysis for “split-phase” switching is also presented in detail, without making small ripple approximations. Furthermore, an expression for large ripple flying capacitor energy density utilization is derived, assisting with optimal topology selection and revealing that split-phase operation may be preferable for conversion ratios greater than 6:1. All analysis is verified in simulation, with an additional discrete hardware prototype further validating a complex case of resonant split-phase timing. The analytical results of 17 distinct Dickson variations are recorded, assisting with topology selection and design.

Optimal Sizing and Locations of Capacitors Using Slime Mould Algorithm

A new and powerful approach called Slime Mould Algorithm (SMA) is suggested in this paper, for optimal siting and sizing of capacitors for an IEEE distribution network. First, the most nominee buses for installing capacitors are developed using various indices. Loss Sensitivity Factors (LSF), Voltage Stability Index (VSI), and Power Loss Index (PLI) are employed to determine the selected buses. Then the proposed SMA is used to deduce the size of capacitors and their positions from the picked buses. The objective function is introduced to minimize the net cost and then, increase the total saving per year. The developed approach is tested on the IEEE distribution network. The obtained results are compared with others to highlight the advantages of the developed approach. Also, the results are presented to confirm its influence in minifying the losses, and net cost and to improve the voltage profile and total saving for a radial distribution network.

Size Estimation of Bulk Capacitor Removal Using Limited Power Quality Monitors in the Distribution Network

With a large number of distributed generators (DG) and sensitive power loads connected to the distribution network, power quality issues have increasingly become the focus of users’ attention. Accurate and quick estimation of the amount of bulk capacitor removal that causes voltage sag is helpful to maintain power quality management equipment in time. This paper presents a novel size estimation of bulk capacitor removal using a limited power quality monitor (PQM) in the distribution network, including PQM deployment optimization, feeder localization, and capacitor removal amount calculation. The PQM placement is optimized by taking the estimated capacitance removal sizes of all buses as a constraint. The change of reactive power consumption before and after removing the capacitor at each power line is adopted to determine the feeder where the disturbance is located. Based on the impedance characteristics of the power grid components, the steady estimation method (SEM) is deduced using the fundamental voltage and current. Applying the sampling points of instantaneous voltage and current waveform, the transient estimation method (TEM) is constructed by data fitting. Case studies and index analysis for the IEEE 13 bus test work are presented to verify the reasonableness and accuracy of the proposed method for disturbed bus, capacitor size, load symmetry, disturbance duration, and DGs. SEM shows more stability and accuracy, while TEM performs faster and is more robust. The new methods provide a reliable and acceptable disturbance size estimation with several limited PQMs.

Double-integral sliding mode control of the switched-inductor quasi-Z source boost converter

Compared with the traditional converter, the switching inductance quasi-Z source DC-DC boost converter has the characteristics of wide output voltage, small capacitor size and more reliable circuit. However, in the process of DC voltage boost, the system is prone to high startup impulse voltage, output voltage fluctuation, and other problems. Therefore, a double integral sliding mode control (DISMC) method is proposed. The control method takes the capacitance voltage error, the inductance current error and their sum of single integral and double integral as state variables, and derives the equivalent control law from the sliding mode surface. A Lyapunov function is constructed to analyze the existence conditions of DISMC method. And the effects of abrupt changes of input voltage, negative reference voltage and load power on transient oscillation, steady state error and overshoot of the system are analyzed. This control method solves the non-minimum phase problem of capacitor voltage, so as to improve the start-up performance of the controller and speed up the response of the system. Finally, the superiority and effectiveness of the control method are verified by simulation.

Low Operating Voltage, Improved Breakdown Tolerance, and High Endurance in Hf0.5Zr0.5O2 Ferroelectric Capacitors Achieved by Thickness Scaling Down to 4 nm for Embedded Ferroelectric Memory

The comparatively high coercive field in Hf0.5Zr0.5O2 (HZO) and other HfO2-based ferroelectric thin films leads to two critical challenges for their application in embedded ferroelectric memory: high operating voltage due to a large thickness-field product and poor endurance due to the high operating field close to the breakdown field. In this study, we demonstrate that the thickness scaling of ferroelectric HZO down to 4 nm is a promising approach to overcome these challenges. As the coercive voltage scales down almost linearly with the film thickness, the operating voltage of 4 nm HZO is reduced to 0.6 V for one-shot operation and 1.2 V for stable memory operation, which is in the voltage range compatible with scaled silicon technologies. Furthermore, it is found that the breakdown field is substantially improved in thinner HZO since the breakdown mechanism is dominated by the stress voltage, not the stress field, resulting in improved cycle-to-breakdown by more than 4 orders of magnitude when thinning from 9.5 to 4 nm. We identify two concerns accompanying thickness scaling: the increase in crystallization temperature and the pinched hysteresis behavior, which can be addressed by carefully preparing temperature-thickness mapping and applying strong-field wake-up cycling, respectively. Our optimal 4 nm-thick HZO ferroelectric capacitor exhibits an operating voltage of 1.2 V with over 10 year data retention and 1012 endurance cycles at 100 kHz, which can be further improved to more than 1014 with a smaller capacitor size and higher operating frequency.

Reduced Capacitor Energy Requirements in Battery Energy Storage Systems Based on Modular Multilevel Converters

Battery energy storage systems (BESS) based on modular multilevel converters (MMCs) allow battery packs to be integrated into the electrical grid in a modular fashion. Inherent to the operation of the MMC, the module's dc-link capacitor voltage experiences oscillations at grid frequency and its harmonics. This article investigates the close relation between this voltage oscillation and the battery current ripple. The precise capacitor energy requirements for various operations of BESS-MMC, which include arm/phase power balancing and state-of-charge balancing are analyzed in this article. Furthermore, this article also explores the relation between the controller design and the submodule's (SMs) capacitor sizing in terms of its energy requirements. Design guidelines for the SM level voltage control to attenuate battery ripple and detailed analysis for the capacitor energy requirement in each operating mode are presented. The control and capacitor sizing design are validated in real-time using embedded microprocessors in a Typhoon-based controller hardware-in-the-loop environment.

Enhancement of Voltage Stability by Optimal Placement of Shunt Compensation using Bus Voltage Stability Indices and Reactive Power Margin

Voltage stability problem has caused several blackouts in many countries in recent years. Impending voltage instability has been a significant threat to modern power system's security and reliability. Moreover, the operation and planning of large interconnected power systems is becoming increasingly complex as power demand rises, posing a security risk to the grid. Appropriate efforts to improve power system security and increase voltage stability margin should be planned to keep the system secure. This work investigates the voltage stability of a power system with and without a shunt capacitor. The bus voltage stability index, L index, is used to measure the distance of the power system to its stability limit in order to assign the shunt capacitor. The L-index for a particular load state is computed for all load buses, and the greatest L-index indicates the system's approach to voltage collapse. The system's load ability margin is being traced utilizing a static voltage stability evaluation approach, i.e., PV and QV curve analysis. The minimal power loss approach is used to calculate the optimal capacitor size. The effect of shunt compensation was simulated, and the results with and without compensation were compared. The IEEE-9 bus system was employed in this work, and the system was simulated using MATLAB and Power World Simulator. The result demonstrates that the shunt capacitor enhances voltage stability by injecting the appropriate reactive power.