Optimization-Based Methodology to Design the MMC's Sub-Module Capacitors

Abstract

This paper proposes an optimization-based size reduction methodology for Modular Multilevel Converters (MMC), focusing on minimizing the converter's sub-module capacitor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_{SM}$</tex-math></inline-formula> . The analysis is performed considering both the converter's current and voltage limitations and the Transmission System Operator (TSO) Fault Ride Through (FRT) requirements. By means of a steady-state analysis, the time-domain expressions of the converter's arms energies are obtained and their behavior throughout the MMC's operating range is shown. Based on these expressions, the optimization-based problem to reduce the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C_{SM}$</tex-math></inline-formula> size is developed and its constraints are imposed to ensure that the converter's voltage and current levels are within its design limitations. The suggested method is compared with different approaches for distinct active and reactive power set-points, where it is shown that the SM capacitor size can be reduced up to 24% in comparison with the method with worst performance and up to 7% regarding the best method used for comparison purposes. Furthermore, time-domain simulations of the MMC considering several AC voltage sags are performed in order to demonstrate that the dynamics of the SM capacitor and the arm applied voltages are within acceptable margins during the different operations.