Single Transistor Research Articles

Blue Phosphorene Bilayer Is a Two-Dimensional Metal and an Unambiguous Classification Scheme for Buckled Hexagonal Bilayers.

High-level first-principles computations predict blue phosphorene bilayer to be a two-dimensional metal. This structure has not been considered before and was identified by employing a block-diagram scheme that yields the complete set of five high-symmetry stacking configurations of buckled honeycomb layers, and allows their unambiguous classification. We show that all of these stacking configurations are stable or at least metastable both for blue phosphorene and gray arsenene bilayers. For blue phosphorene, the most stable stacking arrangement has not yet been reported, and surprisingly it is metallic, while the others are indirect band gap semiconductors. As it is impossible to interchange the stacking configurations by translations, all of them should be experimentally accessible via the transfer of monolayers. The metallic character of blue phosphorene bilayer is caused by its short interlayer distance of 3.01Å and offers the exceptional possibility to design single elemental all-phosphorus transistors.

Multi‐mode fault‐tolerant control strategy for cascaded H‐bridge multilevel inverters

This study proposes a multi-mode fault-tolerant control (FTC) strategy, for cascaded H-bridge multilevel inverters, to provide the most suitable fault tolerance scheme for different single or double arbitrary insulated gate bipolar transistor (IGBT) faults. Firstly, all faulty modes are classified into three fault clusters according to the number and location of faulty IGBTs. Then, the matching mechanism of the multi-mode FTC strategy corresponding to the three clusters is described, and the appropriate FTC algorithm is selected for each cluster. In particular, a new FTC method has been proposed for Cluster I that includes double IGBT fault in different H-bridges and different groups. This method improves the utilisation efficiency of healthy IGBTs in the faulty H-bridges, and minimises the voltage level drop after the fault. Finally, the multi-mode FTC strategy has been applied to a seven-level inverter through simulation. Results have shown significant improvement of the output voltage waveform symmetry and harmonic distortion reduction for the three clusters. The new FTC method has been applied to an experimental five-level inverter. The obtained results confirm the validity of the methodology. With the proposed strategy, the output voltage has a lower harmonic distortion and a better symmetry thanks to the attenuation of the undesirable DC component.

Prediction of a Two-Transistor Vertical QNOT Gate

A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors.

On the Influence on the Operation of the Quadrated Transistor of Short Circuits between the Gate of a Single Transistor, its other Outputs and the Power Source

The influence on the operation of the quadrated transistor of short circuits between the gate of the field transistor and its other outputs (source, drain, substrate) and also its power source with input signals 0 and 1 on the gate for two variants of the quadrated transistor circuit is considered. It is shown that in an overwhelming number of cases the result at the output of the quadrated transistor is correct.

Room temperature terahertz detector based on single silicon nanowire junctionless transistor with high detectivity

In this work, the n-type single silicon nanowire (NW) based junctionless field-effect transistor (FET) is demonstrated as an efficient terahertz (THz) detector. For the effective coupling of the THz radiations with NW junctionless FET, the lobes of the rounded bow-tie antenna are connected to the gate and source terminals of the device. The antenna design is optimized with proper impedance matching conditions to achieve maximum power transfer between antenna and detector. The simulated antenna resonates at 0.43 THz frequency with 19 GHz bandwidth. Further simulations have been done on Lumerical finite difference time domain software to analyze the electric field distribution profile. To investigate the optical response of this optimized antenna design, an array of the simulated antenna has been fabricated and its transmission spectra are measured. Finally, the simulated antenna has been integrated with the n-type NW junctionless transistor. A maximum responsivity of 468 V W−1 at 0.425 THz frequency and noise-equivalent-power of ∼ 10−9W/Hz1/2 is obtained at room temperature. The complementary metal-oxide-semiconductor’s compatibility, ease of integration on chips, possibility to realize multiple pixel arrays, andscalability to higher frequencies, make this device promising for THz electronics.

Design and Investigation of Split-Gate MoTe2-Based FET as Single Transistor AND Gate Using Nonequilibrium Green’s Function

Failure of metal–oxide–semiconductor field-effect transistor (MOSFET) in the nanometer regime has raised concern for the researchers. Although researchers have provided solutions in the form of tunnel FETs and junctionless transistors but due to their fabrication issues, MOSFET remains as the backbone of the very large-scale integration (VLSI) industry. This work is dedicated to the design and study of the novel split-gate MOSFET made up of transition metal dichalcogenide. The proposed design can help in realizing digital gates because the device is used as a single transistor AND gate in this work. The device is analyzed for different conditions like the variation in work function, variation in gate length, variation in spacer oxide, and effect of interface trap charge (ITC) density. Nonequilibrium Green’s Function is used as an elemental model of the transistor to include quantum effects for scaled-down dimensions. This work shows that the proposed device results in a noticeable flow of current only when both the gate terminals are at higher potential, that is, at state “11.” The observed linearity is good enough for the efficient working of the device. Hence, the device can be utilized as AND gate with a lesser area and power dissipation.

Random-telegraph-noise-enabled true random number generator for hardware security

The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

Nonuniformity-Immune Read-In Integrated Circuit for Infrared Sensor Testing Systems

In this study, a novel IR projector driver that can minimize nonuniformity in electric circuits, using a dual-current-programming structure, is proposed to generate high-quality infrared (IR) scenes for accurate sensor evaluation. Unlike the conventional current-mode structure, the proposed system reduces pixel-to-pixel nonuniformity by assigning two roles (data sampling and current driving) to a single transistor. A prototype of the proposed circuit was designed and fabricated using the SK-Hynix 0.18 µm CMOS process, and its performance was analyzed using post-layout simulation data. It was verified that nonuniformity, which is defined as the standard deviation divided by the mean radiance, could be reduced from 21% to less than 0.1%.

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness ( ${T}_{{\text {Si}}}$ ) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.

Investigation of f T-Doubler Technique to Improve RF Performance of Inverse-Mode SiGe HBTs

This letter presents the application of the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler technique, for the first time, to improve the unitygain frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of inverse-mode (TM) silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). An f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler structure, which used three identical SiGe HBTs with the same emitter area of 0.07 (width) × 0.9 (length) μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , is implemented in a commercial 0.13-μm SiGe-BiCMOS technology platform. A peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 77 GHz is extrapolated for the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> doubler, whereas a peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of a single TM SiGe HBT is found to be 53 GHz, exhibiting an increase of about 46% in f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> from the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler technique. The maximum oscillation frequency of the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> doubler using Mason's unilateral gain is about 158 GHz. Tn addition, small-signal model parameters of the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> doubler are presented, which show the TM f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -doubler structures can be treated as a single transistor element for highfrequency circuit design.

Dynamic behavioral modeling of RF power amplifiers based on decomposed piecewise machine learning technique

AbstractMulti-device radio frequency power amplifiers (PAs) often exhibit strongly non-linear behavior in combination with long-term memory effects, leading to an extremely challenging model development cycle. This paper presents a new, dynamic, behavioral modeling technique, based on a combination of the real-valued decomposed piecewise method and concepts from the field of machine learning. The underlying theory of the proposed modeling technique is provided, along with a detailed modeling procedure. Experimental results show that the proposed decomposed piecewise support vector regression (SVR) model leads to significant performance improvements when compared with standard SVR models for both single transistor and multi-transistor PAs. Different model thresholds are used to test the proposed model performance for both PA types. For the single-transistor PA, modeled using only one partition, an approximately 10 dB normalized mean square error (NMSE) reduction is seen when compared with the standard SVR model. For the same PA, when utilizing two partitions, the reduction improves to 14 dB. When applied to a multi-device Doherty PA, the NMSE between model and measurement data is −50 dB, representing more than 10 dB improvement compared with the standard SVR model.

Vertically Stacked Gate-All-Around Structured Tunneling-Based Ternary-CMOS

This article proposes a novel structure for tunneling-based ternary-complementary metal-oxide-semi conductor (T-CMOS) to break through the power scaling constraints of conventional binary-CMOS. The previous T-CMOS uses off-leakage band-to-band tunneling (BTBT) currents generated at the deep drain-to-substrate junction for the third voltage state, which allows ternary inverter configuration with only two single transistors. However, the high-dose ion implantation for the BTBT layer must affect the channel doping concentration, leading to the threshold voltage fluctuation. To avoid the interference of the BTBT layer dopants to the channel as well as to maximize the electrostatic gate controllability, vertically stacked gate-all-around (GAA) field-effect transistor (GAAFET)-type T-CMOS device is proposed. By simply changing the ground plane (GP) doping concentration in existing GAAFET fabrication, the BTBT layer can be formed completely apart from the suspended channel layers. The changes of the transfer characteristics and the transient output voltage characteristics depending on the key parameters such as the GP doping concentration and the gate work function are thoroughly analyzed for the proposed GAA T-CMOS through mixed-mode TCAD device and circuit simulations. It is concluded that the two key parameters should be optimized, otherwise the margin for the third voltage state and the switching speed is seriously degraded.

A Single Transistor Neuron With Independently Accessed Double-Gate for Excitatory-Inhibitory Function and Tunable Firing Threshold Voltage

For the first time, a single transistor neuron (1T-neuron) with an independently accessed double-gate structure is demonstrated for excitatory-inhibitory-function, and control of the firing threshold voltage (VT,firing). The double-gate is composed of a primary gate and a secondary gate. The former is to determine an excitatory and inhibitory state as a toggle switch and the latter is to dynamically adjust VT,firing for homeostasis to sustain reliable neuromorphic operation. In addition to its conventional excitation function, the newly implemented inhibition function improves the energy efficiency of the neuromorphic network. The tunable threshold voltage for firing maintains homeostasis, even for high or low transmitted signals that are out of a desired spiking frequency range.

Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations

In this paper the performance of different architectures of current mirrors implemented with single SOI transistors and self-cascode transistors, both symmetric and asymmetric is evaluated. A comparison of current mirrors figures of merit, looking for the advantages of the asymmetric composite structure in relation to a single SOI MOSFETs and the symmetric self-cascode transistor is performed. This analysis has been carried out through analytical simulations, using common-source, Cascode and Wilson current mirrors architectures. It is shown that asymmetric configuration can provide larger output resistance even in the common-source current mirror than other architectures with conventional single transistors.

Robust energy-selective tunneling readout of singlet-triplet qubits under large magnetic field gradient

Fast and high-fidelity quantum state detection is essential for building robust spin-based quantum information processing platforms in semiconductors. The Pauli spin blockade (PSB)-based spin-to-charge conversion and its variants are widely used for the spin state discrimination of two-electron singlet–triplet (ST0) qubits; however, the single-shot measurement fidelity is limited by either the low signal contrast, or the short lifetime of the triplet state at the PSB energy detuning, especially due to strong mixing with singlet states at large magnetic field gradients. Ultimately, the limited single-shot measurement fidelity leads to low visibility of quantum operations. Here, we demonstrate an alternative method to achieve spin-to-charge conversion of ST0 qubit states using energy-selective tunneling between doubly occupied quantum dots (QDs) and electron reservoirs. We demonstrate a single-shot measurement fidelity of 90% and an S–T0 oscillation visibility of 81% at a field gradient of 100 mT (~500 MHz h (g*·μB)−1); this allows single-shot readout with full electron charge signal contrast and, at the same time, long and tunable measurement time with negligible effect of relaxation even at strong magnetic field gradients. Using an rf-sensor positioned opposite to the QD array, we apply this method to two ST0 qubits and show high-visibility readout of two individual single-qubit gate operations is possible with a single rf single-electron transistor sensor. We expect our measurement scheme for two-electron spin states can be applied to various hosting materials and provides a simplified and complementary route for multiple qubit state detection with high accuracy in QD-based quantum computing platforms.

Temperature-switching logic in MoS2 single transistors**Project supported by the National Natural Science Foundation of China (Grant Nos. 61925402, 61851402, and 61734003), Science and Technology Commission of Shanghai Municipality, China (Grant No. 19JC1416600), National Key Research and Development Program of China (Grant No. 2017YFB0405600), and Shanghai Education Development Foundation and Shanghai Municipal Education Commission Shuguang Program, China (Grant No. 18SG01).

Due to their unique characteristics, two-dimensional (2D) materials have drawn great attention as promising candidates for the next generation of integrated circuits, which generate a calculation unit with a new working mechanism, called a logic transistor. To figure out the application prospects of logic transistors, exploring the temperature dependence of logic characteristics is important. In this work, we explore the temperature effect on the electrical characteristic of a logic transistor, finding that changes in temperature cause transformation in the calculation: logical output converts from ‘AND’ at 10 K to ‘OR’ at 250 K. The transformation phenomenon of temperature regulation in logical output is caused by energy band which decreases with increasing temperature. In the experiment, the indirect band gap of MoS2 shows an obvious decrease from 1.581 eV to 1.535 eV as the temperature increases from 10 K to 250 K. The change of threshold voltage with temperature is consistent with the energy band, which confirms the theoretical analysis. Therefore, as a promising material for future integrated circuits, the demonstrated characteristic of 2D transistors suggests possible application for future functional devices.

An Atomically Thin Optoelectronic Machine Vision Processor

2D semiconductors, especially transition metal dichalcogenide (TMD) monolayers, are extensively studied for electronic and optoelectronic applications. Beyond intensive studies on single transistors and photodetectors, the recent advent of large-area synthesis of these atomically thin layers has paved the way for 2D integrated circuits, such as digital logic circuits and image sensors, achieving an integration level of ≈100 devices thus far. Here, a decisive advance in 2D integrated circuits is reported, where the device integration scale is increased by tenfold and the functional complexity of 2D electronics is propelled to an unprecedented level. Concretely, an analog optoelectronic processor inspired by biological vision is developed, where 32 × 32 = 1024 MoS2 photosensitive field-effect transistors manifesting persistent photoconductivity (PPC) effects are arranged in a crossbar array. This optoelectronic processor with PPC memory mimics two core functions of human vision: it captures and stores an optical image into electrical data, like the eye and optic nerve chain, and then recognizes this electrical form of the captured image, like the brain, by executing analog in-memory neural net computing. In the highlight demonstration, the MoS2 FET crossbar array optically images 1000 handwritten digits and electrically recognizes these imaged data with 94% accuracy.

Design of low power 16-bit counter with Programmable Combinational Logic and Integrated Clock Gating using 16-nm technology

ABSTRACT To demand high power back up by increasing the user’s need for applications in a single IC, the power dissipation takes place. The proposed two approaches are control Logic (CL) with Integrated Clock Gating (ICG) and Programmable Combinational Logic(PCL)and Gate Logic(GL) with ICG to achieve the low power and low dynamic leakage in 16-bit Counter. These approaches operate in different Logic to Generate/stop the clock for low-power digital circuits. The First approach of control Logic with ICG stops the clock only for single Most Significant Flip Flop Transistor. This approach consumes 1.6 mW and 15% more power savings than Existing. But the second approach only consumes 0.0261 mW power, which is 98% more power savings than a first proposed approach of CL with ICG and conventional counters. These dramatic boom power savings by stopping the clock for all redundant transition in Most Significant Flip Flop Transistors using PCL & GL with ICG. Analyse the second approach without ICG for 16-bit counter will consume 0.0334 mW, which consumes 21.96% high power than the presence of ICG in counter circuits. Moreover, the same proposed technique of the second approach applies for ISCAS’89 S444 circuits, which saves >90% power improvement than the conventional method and ordinary 16-bit counter-power analysis by the same technology, which consumes 42.42% high power than proposed low-power counter. The Low Power 16-bit counter design implementation using 16 nm Cadence Genustechnology, which attains the dynamic leakage with ICG is 0.170nW and without ICG is 0.177nW with an operating voltage of 0.8 V.

Liquid-Loaded Piezo-Silicon Micro-Disc Oscillators for Pico-Scale Bio-Mass Sensing

In this work, we report on the implementation of a closed-loop liquid-loaded resonant mass sensor as a test vehicle for the realization of highly sensitive miniaturized biomarker assays. Using thin-film piezoelectric-on-silicon (TPoS) contour-mode disc resonators that are specifically designed and optimized for liquid-phase operation, a liquid-loaded low power (~1.6 mW) oscillator at ~17 MHz is demonstrated with a single transistor. By proper placement of the electrodes and the supporting tethers, a high liquid-loaded quality factor (~380) and a low insertion loss (~19 dB) are concurrently achieved which enable the accurate frequency tracking of the potential mass microbalance. The frequency shifts due to the liquid-loading and the preliminary characterized frequency stability of the oscillator imply a minimum mass detection resolution in the picograms range. [2020-0177]

Switching Behavior in a Vertical Tunneling Transistor by Tunneling Mechanism Transition and Floating Electrode Structure

Direct application of the tunneling mechanism into the conventional field-effect transistor structure only results in inefficient switching behavior and high leakage current. Here, we report a vertical metal–insulator–metal (MIM) tunneling transistor employing a floating electrode to achieve an efficient switching behavior and substantially low leakage current simultaneously. This switching method utilizes a tunneling mechanism transition between direct and Fowler–Nordheim tunneling by placing the floating electrode into a vertical tunneling channel. Engineering the electrical potential of the floating electrode with coplanar dual gates enables the efficient control of the tunneling mechanism transition. This particular arrangement of the gate and source/drain (no overlap) allows an extremely low gate leakage current (∼10–13 A). This value is significant in the tunneling transistor and promising for future electrical devices with low-power consumption. Furthermore, tunneling, whose operating principle is fundamentally different from the p–n junction and Schottky barrier in the Si transistor, has been proposed as a solution to tackle the issues such as high-frequency driving, power consumption, and so on. This structure is a strong candidate for ultrahigh-frequency driving because of its extremely low structural capacitance (∼1.5 zF). An additional electrical status can be shown to generate ternary or more statuses in a single transistor. Its electrical performance is expected to not only harmonize with THz communication systems, control process units, and high-speed electrical systems but also contributes a degree of integration. Moreover, the simple and low-temperature fabrication process of the vertical MIM tunneling transistor is advantageous for low-cost electrical devices and flexible electronic applications.