Prediction of a Two-Transistor Vertical QNOT Gate

Heesung Han,Chang-Hyun Kim

doi:10.3390/app10217597

Abstract

A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors.

Highlights

The current electronics era was made possible by digital systems that maximize their simplicity in converting, processing, and memorizing a wide range of data into only two available electrical signal levels (“0” and “1”)
Such a standard binary logic architecture seems to hardly meet the increasing requirements for larger information capacities, which laid out the foundation of multi-valued logic (MVL) systems with n ≥ 3, where n is the number of distinguishable data levels [1,2,3]
We demonstrate an aggressive projection of quaternary (n = 4) digital inverter made of only two field-effect transistors (FETs), by carrying out physically based finite-element simulation

Summary

Introduction

The current electronics era was made possible by digital systems that maximize their simplicity in converting, processing, and memorizing a wide range of data into only two available electrical signal levels (“0” and “1”). Such a standard binary logic architecture seems to hardly meet the increasing requirements for larger information capacities, which laid out the foundation of multi-valued logic (MVL) systems with n ≥ 3, where n is the number of distinguishable data levels [1,2,3]. For a higher n, previous research mostly adopted circuit-based implementations with the number of transistors roughly corresponding to the number of data levels [10,11], implying the huge technological interest in advanced designs that reduce the transistor count

Methods

Results

Conclusion