Single Transistor Research Articles

Two-Stage Design of High Power UWB Monocycle Generator for Radar Sensor Applied in The Fourth Industry Revolution

This paper presents a high power monocycle generator for Radar Sensor detection in IoT application. The generator was made up of three essential parts-circuits, an avalanche transistor, an Step Recovery Diode (SRD) pulse sharping and an Monocycle Forming Network (MFN). The main idea in this work is to generate a high power monocycle pulse with a minimum of ringing in the output waveform. To overcome this challenge, a useful technique consists of introducing a twice stage of the transistor after the triggering with an overvoltage. The measurement results give an output waveform of 2.3 volts in amplitude with a minimum ringing around 3.6% in overshoot at 1 MHz, which is nearly fourfold of the peak power produced by a single transistor. The generator circuit is completely fabricated using microstrip structure technology characteristics. Good agreements between the measured and theoretical results are achieved which can consider very attractive in many application fields.

Enhanced ambipolar charge transport for efficient organic single crystal light-emitting transistors with a narrowed ambipolar regime

An efficient ambipolar OLET was constructed based on a high-mobility emissive 2,6-diphenylanthracene semiconductor via energy-level engineering, giving a narrowed ambipolar regime with strong light emission.

Characteristics of hydrogen-terminated single crystalline diamond field effect transistors with different surface orientations

Diamond has great potential applications in high-power, high-frequency semiconductor devices because of its wide band gap (5.5 eV), high thermal conductivity (22W/(cm·K)), and high carrier mobility (4500 cm<sup>2</sup>/(V·s) for electron, and 3800 cm<sup>2</sup>/(V·s) for hole). It has been widely considered as an ultimate semiconductor. From the analysis of our previous work, we find that the output current of field effect transistor based on hydrogen-terminated polycrystalline diamond is usually larger than that based on single crystal diamond, and that the preferential orientations of the polycrystalline diamond are mainly <inline-formula><tex-math id="Z-20200108113531-1">\begin{document}$ \langle 110\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-1.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-1.png"/></alternatives></inline-formula> and <inline-formula><tex-math id="Z-20200108113531-2">\begin{document}$ \langle 111\rangle $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-2.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="2-20191013_Z-20200108113531-2.png"/></alternatives></inline-formula> shown by XRD results. Therefore, in order to further analyze the effect of surface orientation on the device performance of hydrogen-terminated diamond field effect transistor (FET), we study the devices fabricated respectively on the (110) plane and (111) plane single crystal diamond plates obtained from a single 3.5-mm-thick single crystal diamond grown by the microwave plasma chemical vapor deposition on the high-pressure high-temperature synthesized diamond substrate. Prior to processing the device, these diamond plates are characterized by atomic force microscope, Raman spectra and photoluminescence (PL) spectra. The results of Raman and PL spectra show that (110) plane and (111) plane plates originating from the same CVD single crystal diamond have no significant difference in optical property. Then the normally-on hydrogen-terminated diamond FET with a gate length of 6 μm is achieved. The device on (111) plane delivers a saturation drain current of 80.41 mA/mm at a gate voltage <i>V</i><sub>GS</sub> = –4 V, which is approximately 1.4 times that of the device on (110) plane. Meanwhile, the on-resistance of the device on (111) plane is 48.51 Ω·mm, and it is only 67% of the device on (110) plane. Analyses of the capacitance-voltage show that the hole concentration of the gated device on (110) plane and (111) plane are 1.34 × 10<sup>13</sup> cm<sup>–2</sup> and 1.45 × 10<sup>13</sup> cm<sup>–2</sup>, respectively, approximately at the same level. In addition, the hole density of the device on both (110) and (111) plane increase near-linearly with the increase of gate voltage from the threshold voltage to – 4 V, indicating that the control effect of the gate on the carrier in the channel is uniform. The possible reason for the higher saturation drain current as well as the lower on-resistance of the device on (111) plane is that its sheet resistance is lower.

Asymmetric organic semiconductors for high performance single crystalline field-effect transistors with low activation energy

We synthesized three asymmetric anthracene derivatives, in which 2-phvA shows a high field-effect mobility of 10 cm2 V−1 s−1. This work demonstrates the potential advantages of asymmetric structures for high-performance organic semiconductors.

Single donor transistors with nanochannels and role of dielectric confinement

Single donor transistors with nanochannels and role of dielectric confinement

Under-FET Thermal Sensor Enabling Smart Full-Chip Run-Time Thermal Management

This article reports design, fabrication and analysis of a novel under-transistor (under-FET) in-hole thermal sensor diode structure. Being able to accurately monitor self-heating of individual transistor in-operando, the under-FET temperature sensor enables smart full-chip run-time thermal management with spatial resolution down to single transistor level. The in-hole thermal sensors were fabricated in a CMOS process and validated in measurements. The new chip level thermal management technique was demonstrated using a prototype power amplifier (PA) IC designed in a foundry 40nm CMOS. It opens a door for self-learning based full-chip real-time intelligent thermal management for future ICs.

Single transistor RC‐only second‐order allpass filters

SummaryIn this letter, all possible single transistor RC‐only second‐order allpass filters obtainable from a four impedance common‐source topology are reported. It is shown that there are only seven such filters with only one of them being a minimum component canonical 2R‐2C filter. Two of the found filters are designed and simulated in a 65‐nm CMOS process.

Solution-Processed, Electrolyte-Gated In2O3 Flexible Synaptic Transistors for Brain-Inspired Neuromorphic Applications.

Emulating the essential synaptic behaviors using single synaptic transistor has attracted extensive attention for building the brain-inspired neuromorphic systems. However, few reports on synaptic transistors fabricated by solution processes have been reported. In this article, the indium oxide synaptic transistors based on polyimide substrates were fabricated by a nontoxic water-inducement method at a low temperature, and lithium perchlorate (LiClO4) was dissolved in polyethylene oxide as the gate electrolyte. For water-inducement process, comparable electrical properties of the synaptic transistors can be achieved by prolonging the annealing time rather than high-temperature annealing with a relatively short time. The effect of the annealing time on the electrical performance of the electrolyte-gated transistors annealed at various temperatures was investigated. It is found that the electrolyte-gated-synaptic transistor on polyimide substrate annealed at 200 °C exhibits high electrical performance and good mechanical stability. Due to the ion migration relaxation dynamics in the polymer electrolyte, various important synaptic behaviors such as the excitatory postsynaptic current, paired-pulse facilitation, high-pass filtering characteristics, and long-term memory performance were successfully mimicked. The electrolyte-gated synaptic transistors based on solution-processed In2O3 exhibit great potential in neuromorphological applications.

Local impact of Stone–Wales defect on a single layer GNRFET

In this work, a new structure of single layer armchair graphene nanoribbon field effect transistor with the Stone–Wales (SW) defect (SWGNRFET) is studied. The simulations are solved with Poisson–Schrödinger equation self-consistently by using Non-Equilibrium Green Function (NEGF) and in the real space approach. The energy band structure is obtained by approximation tight-binding method. The results show that displacement of a defect in the width of the channel of the new structure is led to 50% increase in ION/IOFF ratio only by rotating of a C–C (Carbon–Carbon) bond with similar behavior. But, a remarkable increase of 300% in ION/IOFF ratio is obtained by a “dual center” defect. The results show that structure with defects in the middle of the channel, has the best performance of SWGNRFET. On the other hand, ION/IOFF ratio decreases when the defect moves from middle to the “near the drain” and “source”.

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Analysis of Al0.15Ga0.85N/GaN/Al0.15Ga0.85N DH-HEMT for RF and Microwave Frequency Applications

A charge control based analytical model is followed to study the impact of donor-layer doping and gate-length on microwave frequency performance of AlGaN/GaN/AlGaN double heterostructure high electron mobility transistor (DH-HEMT). DH-HEMT is observed to be more sensitive to gate-length and doping variation as compared to single heterostructure high electron mobility transistor (SH-HEMT). The effect of gate-length and doping on various performance parameters, i.e., transconductance, drain conductance, cut-off frequency and maximum oscillation frequency has been analysed. The results so obtained are compared with simulation results and are found to be in good agreement.

Особенности проектирования многоразрядных КМОП-КНИ-АЦП для создания многоканальных высокоскоростных систем ЦОС с повышенной сбоеустойчивостью

The features and possibilities of using foreign and domestic foundry technologies in the creation of CMOS-ADC for high-speed multichannel DSP systems with increased fault resistance to the effects of TKCH are considered. The architecture and technique of ADC balancing, which provide an increase in the conversion rate when several ADCS operate in the alternating mode, are presented. The technique of double reservation of sources of «weight» currents is considered. The necessity of using an additional current source and dual series-connected CMOS transistors instead of single transistors of the same conductivity type is substantiated. It is noted that the proposed solutions provide effective amortization of the impact of TKCH with the most "dangerous" energies of 20-100 MeV/nucleon

Velocity Saturation Effect on Low Frequency Noise in Short Channel Single Layer Graphene Field Effect Transistors

Graphene devices for analog and RF applications are prone to Low Frequency Noise (LFN) due to its upconversion to undesired phase noise at higher frequencies. Such applications demand the use of short channel graphene transistors that operate at high electric fields in order to ensure a high speed. Electric field is inversely proportional to device length and proportional to channel potential so it gets maximized as the drain voltage increases and the transistor length shrinks. Under these conditions though, short channel effects like Velocity Saturation (VS) should be taken into account. Carrier number and mobility fluctuations have been proved to be the main sources that generate LFN in graphene devices. While their contribution to the bias dependence of LFN in long channels has been thoroughly investigated, the way in which VS phenomenon affects LFN in short channel devices under high drain voltage conditions has not been well understood. At low electric field operation, VS effect is negligible since carriers velocity is far away from being saturated. Under these conditions, LFN can be precicely predicted by a recently established physics-based analytical model. The present paper goes a step furher and proposes a new model which deals with the contribution of VS effect on LFN under high electric field conditions. The implemented model is validated with novel experimental data, published for the first time, from CVD grown back-gated single layer graphene transistors operating at gigahertz frequencies. The model accurately captures the reduction of LFN especially near charge neutrality point because of the effect of VS mechanism. Moreover, an analytical expression for the effect of contact resistance on LFN is derived. This contact resistance contribution is experimentally shown to be dominant at higher gate voltages and is accurately described by the proposed model.

Magneto-transport properties of a single molecular transistor in the presence of electron-electron and electron-phonon interactions and quantum dissipation

A single molecular transistor is considered in the presence of electron-electron interaction, electron-phonon interaction, an external magnetic field and dissipation. The quantum transport properties of the system are investigated using the Anderson-Holstein Hamiltonian together with the Caldeira-Leggett model that takes care of the damping effect. The phonons are first removed from the theory by averaging the Hamiltonian with respect to a coherent phonon state and the resultant electronic Hamiltonian is finally solved with the help of the Green function technique due to Keldysh. The spectral function, spin-polarized current densities, differential conductance and spin polarization current are determined.

Modeling and analysis for the effects of gamma irradiation on the DC and AC performance in InGaP/GaAs SHBTs

ABSTRACTThe effects of gamma irradiation on the DC and AC characteristics of InGaP/GaAs single heterojunction bipolar transistors (SHBTs) are investigated comprehensively for the first time, which is based on experimental data before irradiation, after irradiation and after annealing. A simplified VBIC device model is developed to describe the DC and AC characteristics of the devices. The model parameters are extracted from experimental data before irradiation, after irradiation and after annealing. Finally, the degraded rates of model parameters are used to study the radiation-induced degradation of the device performance.

DC measurement of dressed states in a coupled 100 GHz resonator system using a single quasiparticle transistor as a sensitive microwave detector

We report on the on-chip detection of microwaves in the frequency range around 100 GHz. For the purpose of detection, we employ a discrete transport channel triggered in a superconducting single-electron transistor by photon-assisted tunneling of quasiparticles. The technique is applied to observe the spectrum of the dressed states of a model circuit quantum electrodynamics system consisting of a superconducting coplanar resonator coupled to a Josephson oscillator. The dressed states appear as typical resonance anticrossing exhibiting, in our case, an expectedly wide frequency splitting corresponding to the Jaynes–Cummings coupling strength, g/π∼ 10 GHz. Due to the high decay rate, γ∼ 20–40 GHz, in the very transparent Josephson junctions used, the strong coupling limit, g≫γ, which is required for qubit operation, is not achieved, and the photon population in the resonator is low, ⟨n⟩< 1. Remarkably, the continuous readout of the low population states demonstrates the high microwave sensitivity of the detector.

The Unconventional Influence of a Nearby Molecule onto Transport of Single C60 Molecule Transistor**Supported by the National Key R&D Program of China (2016YFA0200800), the Strategic Priority Research Program of Chinese Academy of Sciences under Grant Nos XDB30000000 and XDB07030100, the Sinopec Innovation Scheme (A-381), and the Rise-Sinopec Fund (No 10010104-18-ZC0609-0003).

We study the transport property of single C60 molecular transistors with special focus on the situation that other molecules are in vicinity. The devices are prepared using electromigration and thermal deposition techniques. Pure single C60 molecule transistors show typical coulomb blockade behavior at low temperature. When we increase the coverage of molecules slightly by extending the deposition time, the transport spectrum of devices displays a switching behavior in the general coulomb blockade pattern. We attribute this unconventional phenomenon to the influence from a nearby C60 molecule. By analyzing this transport behavior quantitatively based on the parallel-double-quantum-dot model, the interaction from the nearby molecule is proved to be of capacity and tunneling coupling. Thermal stimulation is also applied to the device to investigate the effect of local charging environment variation on intermolecular interaction.

Single-electron transport through single and coupling dopant atoms in silicon junctionless nanowire transistor**Project supported by the National Key R&D Program of China (Grant No. 2016YFA0200503).

We investigated single-electron tunneling through single and coupling dopant-induced quantum dots (QDs) in silicon junctionless nanowire transistor (JNT) by varying temperatures and bias voltages. We observed that two possible charge states of the isolated QD confined in the axis of the initial narrowest channel are successively occupied as the temperature increases above 30 K. The resonance states of the double single-electron peaks emerge below the Hubbard band, at which several subpeaks are clearly observed respectively in the double oscillated current peaks due to the coupling of the QDs in the atomic scale channel. The electric field of bias voltage between the source and the drain could remarkably enhance the tunneling possibility of the single-electron current and the coupling strength of several dopant atoms. This finding demonstrates that silicon JNTs are the promising potential candidates to realize the single dopant atom transistors operating at room temperature.

Versatile model for the contact region of organic thin-film transistors

Abstract Contact effects in organic thin film transistors (OTFTs) remain an important problem to be solved in these devices. Therefore, the correct physio-chemical modeling of the contact regions in OTFTs is necessary. In this work, a versatile model for the contact region of OTFTs is proposed, since it describes the current-voltage characteristics of different kinds of contacts. It reproduces the behavior of Schottky barrier or space-charge limited contacts. It is a simple unified model since only a single parameter is necessary in order to distinguish between both kinds of contacts. The model is easily integrated in a generic compact model for the current-voltage characteristics of OTFTs. The resulting compact model, used in combination with an evolutionary parameter extraction procedure, allows to extract the intrinsic parameters and the current-voltage curves at the contact of single short-channel transistors. There is no need to use transistors with multiple channel lengths to accurately characterize the contact region or the active channel of the transistor. The model is tested with published experimental data of OTFTs with Schottky barrier or space-charge limited contacts. Finally, the method has been used as a diagnostic tool to analyze how an ammonia sensor reacts to different concentrations of the ammonia gas. Interestingly, alterations in the contact region have been detected when the gas concentration varies, transforming the space-charge limited contact of a pristine OTFT into a Schottky barrier contact under the exposure of gas.

Single JFET Front-End Amplifier for Low Frequency Noise Measurements with Cross Correlation-Based Gain Calibration

We propose an open loop voltage amplifier topology based on a single JFET front-end for the realization of very low noise voltage amplifiers to be used in the field of low frequency noise measurements. With respect to amplifiers based on differential input stages, a single transistor stage has, among others, the advantage of a lower background noise. Unfortunately, an open loop approach, while simplifying the realization, has the disadvantage that because of the dispersions in the characteristics of the active device, it cannot ensure that a well-defined gain be obtained by design. To address this issue, we propose to add two simple operational amplifier-based auxiliary amplifiers with known gain as part of the measurement chain and employ cross correlation for the calibration of the gain of the main amplifier. With proper data elaboration, gain calibration and actual measurements can be carried out at the same time. By using the approach we propose, we have been able to design a low noise amplifier relying on a simplified hardware and with background noise as low as 6 nV/√Hz at 200 mHz, 1.7 nV/√Hz at 1 Hz, 0.7 nV/√Hz at 10 Hz, and less than 0.6 nV/√Hz at frequencies above 100 Hz.