Single-phase Power Factor Research Articles

Single-phase online interactive uninterruptible power supply design

The single-phase on-line interactive uninterruptible power supply (UPS) designed in this paper consists of three circuits, namely, a single-phase power factor correction circuit, a single-phase inverter circuit, and a bi-directional DC/DC circuit, each of which contains a main circuit as well as a control circuit. The principle, parameter design and control circuit design of each circuit are briefly described. The simulation model of the UPS is constructed, and the simulation results in normal and abnormal utility power are given to verify the correctness of the design.

Double-Loop Controller Design of a Single-Phase 3-Level Power Factor Correction Converter

This paper presents a study on the double-loop controller design technique for a single-phase power factor correction (PFC) three-level (TL) boost converter. Designing a double-loop controller using conventional methods is challenging due to the 120 Hz voltage ripple in the output voltage. This study proposes new double-loop control design methods using a band-stop filter and MATLAB SISOTOOL, detailed in a step-by-step sequence. A band-stop filter with a 120 Hz stop band is applied to the double-loop controller design. Modeling based on the state-space equation, applicable to the full duty range, is constructed to obtain the transfer function. The double-loop controller structure is then designed, and optimal gains that satisfy the design requirements are obtained through automatic tuning using the MATLAB SISOTOOL library. The simulation results demonstrate the performance of the proposed method, which is further verified by experimental results.

IoT-based Single-Phase Power Factor and Control Panel Monitoring System

The power factor is a value obtained by comparing the actual power value and apparent power in an electric circuit. Because it is related to the quality of the distributed power, this power factor needs to be monitored. Devices with inductive loads generally cause power factor distortion, causing losses. Power factor monitoring is carried out periodically to ensure the efficiency of electricity distribution to the building. Power factor monitoring is usually done on the control panel of a building by measuring the voltage and current flowing. Manual monitoring could be more ineffective in terms of time and effort and has the potential for recording errors. This study proposes a power factor monitoring system on the control panel to facilitate recording. The system created is integrated with IoT technology so that it can monitor and record automatically anywhere and anytime. The developed system has an error percentage of 1.53% for the voltage sensor and 5.02% for the current sensor.

Third-Harmonic-Type Modulation Minimizing the DC-Link Energy Storage Requirement of Isolated Phase-Modular Three-Phase PFC Rectifier Systems

A three-phase ac/dc converter with high-frequency isolation can be realized as a monolithic three-phase or as a phase-modular system by combining three single-phase Power Factor Correction (PFC) rectifier modules with individual isolated dc-dc converters. Advantageously, for a phase-modular system the module configuration can be changed depending on the instantaneous input-output voltage ratio (i.e., a star-(Y)- or a delta-(Δ)-arrangement such that wide voltage ranges can be covered without a massive over-dimensioning of the main power components. However, the main disadvantage of a phase-modular converter realization is the fact that the input power of each PFC rectifier module pulsates at twice the mains frequency (which is inherent to single-phase power conversion) such that large dc-link capacitors are required. Recent literature predicts a substantial power pulsation reduction enabled by means of third-(3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> )-harmonic injection modulation which is applicable for the Y-connection (where a common-mode (CM) / zero-sequence (ZS) voltage is injected), and for the Δ-connection of the three single-phase PFC rectifier modules (where a CM / ZS current is injected). This changes the distribution of the power flow in the three-phase system and the power pulsation is shifted to higher frequencies. This paper experimentally verifies and extends the dc-link energy storage requirement reduction of the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation concept: In a first step, the derivation of the harmonic injection concept is recapitulated and suitable control methods are discussed for both CM voltage (Y-arrangement) and CM current (Δ-arrangement) injection. Further, an alternative CM voltage injection strategy with simplified reference generation based only on the instantaneous grid voltage measurements is presented and compared to the pure 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation. Measurement results obtained from a 6 kW prototype reveal a dc-link voltage variation and/or energy buffering reduction by up to 38.6 % enabled by the harmonic injection modulation compared to conventional operation without 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation.

DC-Link Capacitance Reduction in PFC Rectifiers Employing PI+Notch Voltage Controllers

It is well-known that adding a notch filter in series with the typically employed type-II (or PI) regulator allows improving the tradeoff between dc-link voltage dynamics and grid-side current total harmonic distortion (THD) in practical single-phase power factor correction rectifiers. The article demonstrates that notch filter utilization alternatively allows reducing the value of dc-link capacitance in case hold-up time requirement is absent. The revealed value of minimum capacitance is expressed by explicit function of possible mains frequency values range, maximum expected grid voltage magnitude, rated system power, dc-link voltage set point, maximum tolerable grid-side current THD, and the desired phase margin (PM) of dc-link voltage loop. It is demonstrated that the proposed approach yields fourfold reduction of dc-link capacitance for typical values of 5% tolerable grid-side current THD under 40° PM constraint. Experimental results exhibit close-fitting resemblance to corresponding analytical predictions, verifying the proposed methodology.

Design and Analysis of Zeta Converter for Power Factor Correction Using Cascade PSO-GSA-Tuned PI and Reduced-Order SMC

This paper presents the design and analysis of a single-phase power factor correction (PFC) scheme using a DC–DC Zeta converter operating in continuous conduction mode. The presented DC–DC converter exhibits non-linearity due to switching elements that degrades the performance of the converter. Therefore, this paper proposes a non-linear cascade control of particle swarm optimization-gravitational search algorithm (PSO-GSA) tuned proportional-integral (PI) and sliding mode controller (SMC) in outer and inner loop, respectively, to improve the performance of the converter. The robustness of the controller is analysed by applying the load and line variations to the converter. The simulation results showed that the steady state performance indices such as integral absolute error and integral square error, and transient performance indices like settling time and peak overshoot are significantly enhanced for the proposed cascade control scheme compared to the PSO and root locus method of tuning the outer PI with the inner SMC controller. The proposed control scheme gives better performance in terms of power factor improvement, percentage reduction in total harmonic distortion, and efficient tracking of output voltage for change in reference voltage compared to other techniques presented. Further, the performance of the proposed scheme is tested for battery charging application of the solar photovoltaic system. The demonstrated simulation results are validated by implementing the DC–DC Zeta converter in real-time hardware set-up.

Single-Phase PFC Rectifier With Integrated Flying Capacitor Power Pulsation Buffer

Single-phase Power Factor Correction (PFC) rectifiers with sinusoidal grid currents are inherently subject to an input power fluctuating at twice the mains frequency. In order to potentially mitigate bulky, heavy and failure-prone electrolytic dc-link capacitors, active Power Pulsation Buffer (PPB) concepts are proposed in the literature. For converter systems employing Flying Capacitor (FC) multilevel bridge-legs, the FCs can be utilized as a twice-mains frequency energy storage, i.e., as an integrated active PPB without the need for additional power components. Such ac-dc-stage-integrated FC PPBs capable of buffering the complete input power variation are known in literature which, however, require sophisticated control strategies with varying switching frequency and discontinuous conduction mode. This paper presents a novel ac-dc-stage-integrated FC-PPB approach which is compatible with standard PFC control concepts and enables a significant reduction in dc-link voltage variation. First, a control concept cycling the FC voltage in a wide range without interfering with the grid current controller is derived step by step and verified by means of circuit simulations. Design guidelines for the calculation of suitable FC capacitance values are presented and the limits in buffering capability are discussed. The concept is then experimentally verified with a 2.2kW three-level FC single-phase PFC rectifier employing 600V GaN power semiconductors where the dc-link voltage variation is reduced by 28% compared to conventional operation. Last, the applicability of the ac-dc-stage-integrated FC-PPB concept to other FC converter topologies is discussed.

Differential Mode Noise Prediction and Analysis in Single-Phase Boost PFC for the New Frequency Range of 9–150 kHz

High penetration of power electronics due to the concentration of switching frequency in the range of 9–150 kHz may create new challenging issues. Currently, regarding the recent version standard (IEC 61000-6-3), there is a lack of enough insight and fundamental studies despite reported electromagnetic interference (EMI) noise problems in this frequency range. Hence, this article proposes a time-frequency analytical modeling method for characterizing differential mode (DM) noise in a single-phase power factor correction (PFC) converter in this new frequency range. Provided comparative simulation analysis shows the proposed method's ability to estimate DM noise with a 9–150 kHz frequency range at high accuracy utilizing the double Fourier analysis method. Moreover, the obtained experimental results on a 1-kW single-phase boost PFC converter validate the proposed EMI modeling approach's effectiveness, demonstrating an error of less than 1.8 dB for the considered experimental case studies.

Second Harmonic Current Reduction Schemes for DC–DC Converter in Two-Stage PFC Converters

For the two-stage single-phase power factor correction (PFC) converter, its instantaneous input power pulsates at twice the line frequency, generating the second harmonic current (SHC) at the dc-bus port. The dc–dc stage is used to regulate the output voltage or the dc bus voltage in different applications, and the SHC reduction schemes for the dc–dc stage with different control objectives are discussed in this article. When the dc–dc stage regulates the output voltage, it is pointed out that the control bandwidth of the dc–dc stage is required to be high enough and the dc bus capacitor should be large enough to suppress the SHC, and the design of the dc bus capacitor is given. When the dc–dc stage regulates the dc bus voltage, a virtual impedance is added in series with the input/output of the dc–dc stage to suppress the SHC, and a virtual impedance is added in parallel with the dc bus to improve the dynamic performance. The selection and design of the virtual impedances are also given. Based on that, three specific control schemes are proposed for the dc–dc stage to suppress the SHC, and the parameters design method is also presented. Finally, a 3.3-kW two-stage single-phase PFC converter is fabricated and tested in the lab to verify the effectiveness of the proposed SHC reduction schemes.

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Several techniques to mitigate conducted electromagnetic interference (EMI) in single-phase power factor correction (PFC) converters have been reported in literatures. This paper mainly focuses on the review and classifications of the common-mode (CM) noise mitigation methods based on the novel structures, balance concept, novel modulation methods and so on. Through eliminating the noise generation or cut off the propagation path, those methods can mitigate the CM noise caused by the single-phase PFC converter. Besides, the comparisons and limitations are also discussed. It is believed that this review will be helpful to the design of the EMI filter for the switch-mode power system, which includes the PFC stages.

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Variable Output Voltage Switching Rectifier for Cathodic Protection Applications With DC–DC Variable Frequency and Duty-Cycle Full-Bridge Converter

Rectifiers used in cathodic protection (CP) applications convert ac voltage to variable dc output. This article proposes a switching converter for CP, mostly to enhance the efficiency in low to medium output powers, where the duty cycle is less than 30%. This device is composed of two parts, an ac-dc converter and a dc-dc full-bridge converter. The ac-dc converter is a single-phase boost-type power factor correction converter with emphasis on high efficiency, thus resulting in an almost unity power factor and fixed dc output voltage. The dc-dc full-bridge converter operates under pulsewidth modulation with the simultaneous change of frequency and duty-cycle (SCFD) control method responding to the user output power demand. The SCFD control strategy, in this converter, increases overall efficiency of the proposed rectifier. Finally, a 1875 W prototype is implemented and tested to verify the nearly fixed high efficiency for the converter in a wide operating range of the output power.

Capacitance Requirement Reduction in Single-Phase PFC With Adaptive Injection of Odd Harmonics

This article presents an adaptive harmonic injection approach for single-phase power factor correction (PFC) converters that reduce capacitance requirements and allow the use of smaller and more reliable film capacitors instead of electrolytic capacitors. Many applications require the converter’s rated power only during temporary intervals, whereas most of the time, the output power is much lower. In the proposed approach, the converter operates with a unity power factor below a given output power level. When the output power exceeds this value, then odd harmonics are linearly injected into the input current reference, up to the limits presented by IEC 61000-3-2. This approach reduces the voltage ripple across the power ripple buffering capacitor (PRBC), reducing the required capacitance value. The proposed approach is applied to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> -converter using enhanced automatic power decoupling (EAPD) control. The dynamic model to control PRBC average voltage is presented. A 1-kW prototype is built to validate the approach using a metalized polypropylene film capacitor as the PRBC. At full power, injecting third and fifth harmonics, the PRBC capacitance can be reduced from 22 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15~\mu \text {F}$ </tex-math></inline-formula> or 32%. It represents a further reduction in capacitance requirements for a converter that already requires low capacitance.

Single Phase Power Factor Improvement Based Instantaneous Power P Q Theorm

This paper presents how to harmonic disturbance reduce on single phase power system. One of the most popular method is harmonic signal extraction with instantaneous power p q theorm. This algorithm implemented to harmonic cencellation by active power filter circuit be paralled with the non linier load. This filter generates of current compensation that are injected into the grid to improve power quality. This Filter is built by an inverter circuit that consists of a mosfet switch array and capasitor mounted on DC link side. Two types of loads are resitive inductive and resistive capasitive produce of current source wave form that close pure sinusoid. Simulation results show the THD index fell to the level of 2.7% in accordance with IEEE 519 standard rules which states that the harmonics content of the power system may occur below 4%, indicating that the power system can be categorized as having good quality.

A High-Frequency Power Factor Correction Stage With Low Output Voltage

Single-phase power factor correction (PFC) stages would ideally have three features—operation over the entire line cycle, soft switching at high frequency for all powers and voltages, and a reasonably low output voltage. These features permit high power factor, high combination of density and efficiency, and reduced stress on subsequent stages. Most PFC stages, including the most commonly used, achieve only a subset of these features. Here, we present control innovations to allow a PFC stage to operate from universal input (90–265 Vac) over the entire line cycle with zero-voltage switching (ZVS) with a reduced output voltage. These features are verified with a prototype with very high power factor (> 0.99), high efficiency (98%), and high density (80 W/in3). The PFC can provide an output of 200 Vdc from the entire universal input voltage range which greatly reduces the conversion stress required from subsequent stages. The proposed PFC control consists of a blended feedforward/feedback method that provides additional advantages like guaranteed soft switching, the ability to correct for input capacitance, and the ability to interface with a high-ripple output bus. Therefore, the proposed PFC provides advantages in efficiency and density both for the PFC stage and the overall system.

A Virtual Impedance Based Control Scheme for Modular Electrolytic Capacitor-Less Second Harmonic Current Compensator

The second harmonic current compensator (SHCC) can be added into the single-phase converters for compensating the second harmonic current (SHC) and thus removing the undesired electrolytic capacitor. In this paper, a virtual impedance, which is in the form of a capacitor and a resistor connected in parallel, is introduced to be in parallel at the bus-side port of the SHCC for effectively compensating the SHC while guaranteeing the system stability. This virtual parallel impedance is realized by feeding forward the bus-side port voltage of the SHCC, and thus the SHCC can be modular designed. The closed-loop parameter design of the SHCC is also presented. A 3.3-kW prototype of a two-stage single-phase power factor correction converter is built and tested in the laboratory, and the experimental results verify the effectiveness and feasibility of the proposed control method.

Efficiency and Conducted EMI Evaluation of a Single-Phase Power Factor Correction Boost Converter Using State-of-the-Art SiC Mosfet and SiC Diode

SiC-based diodes and mosfet s switch extremely quickly with low conduction losses. Thus, from the perspective of efficiency, such devices are ideal for a continuous conduction mode (CCM) boost power factor correction (PFC) converter. However, the circuit parasitic becomes alive while switching with high $dv/dt$ and $di/dt$ values, which necessitates the need for electromagnetic compatibility (EMC) compliance measurements. Employing the best available low-loss SiC mosfet and SiC diode, in this paper, a 1-kW PFC boost converter prototype was designed, developed, and evaluated with the objective of quantifying the efficiency and EMC signature. The efficiency is evaluated through two approaches, namely, a circuit simulation and a laboratory measurement. With the first approach, the switching losses are obtained using a widely accepted double-pulse test methodology, and the conduction losses are taken from the data sheet, whereas with the second approach, the current and voltage are recorded at the input and output of the PFC converter using power analyzer. The electromagnetic interference (EMI) is monitored using line impedance stabilizing network and EMC analyzer. To maximize the efficiency, a fast, clean switching of the silicon carbide (SiC) is necessary. Utilizing a low-parasitic printed circuit board design approach and switching the selected low-loss SiC devices with a 0 $\Omega$ external gate drive resistance, this PFC boost yields a peak efficiency of 97.2% at full-rated power when switched at 250 kHz. Furthermore, the EMI noise was measured at 66 and 250 kHz. It was found that the same EMI filter size satisfies the CISPR 11 Class B conducted EMI limit at both switching frequencies with a noise of approximately 10 dB higher at 250 kHz. As the main contribution of this paper, the best case efficiency and worst case EMI are evaluated in this paper.

A Soft-Switching Step-Down PFC Converter with High Power Factor Using Auxiliary Flyback Circuit

In this paper, a new soft-switching bridgeless single-phase power factor correction converter is introduced and analyzed. Employing an auxiliary flyback circuit, existing dead angle in the input current is eliminated while softswitching is achieved. The flyback converter processes only small amount of output power. Therefore, conduction losses of its bridge diode and semiconductor devices are low. Also, the auxiliary flyback converter provides soft-switching condition for buck switches. All semiconductors are turned on and off under soft-switching condition. In addition to reduction of switching losses, diode's reverse-recovery problems are eliminated due to soft-switching condition. The proposed approach takes advantage of operating under discontinuous conduction mode to shape the input current into sinusoidal form inherently. Experimental results are reported for a 120-W prototype at 110 Vrms input and 48-V output. The results demonstrate efficiency of 93% at nominal load condition. Furthermore, the input current harmonics fulfill IEC61000-3-2 (Class D) standard as well.

High‐resolution FPGA‐pulse width modulation applied to PFC 2 MHz converter using eGaN field effect transistor

This study proposes an implementation based on a low-cost field-programmable gate array (FPGA) of a high-resolution pulse width modulation applied on a single-phase power factor correction (PFC) converter operating with 2 MHz switch frequency. The PFC was implemented using a half-bridge enhancement-mode Gallium Nitride (eGaN) field effect transistor with on-board gate drives (EPC9003 development board) and the MAX10 FPGA.

A Single-Phase Three-Level Flying-Capacitor PFC Rectifier Without Electrolytic Capacitors

A component-minimized and low-voltage-stress single-phase power factor correction rectifier without electrolytic capacitor is proposed in this paper. Component minimization is achieved by embedding an active pulsating-power-buffering (PPB) function within each switching period, such that typical add-on power electronic circuits for PPB are no longer needed. Additionally, with a three-level flying-capacitor configuration, the voltage stresses of switching devices can be reduced more than 50% as compared to existing solutions that are based on embedded PPB. The relationship between the inductance requirement and the patterns of the modulation carriers, and how it can be utilized to minimize the magnetics of the rectifier, is also discussed. A 110 W hardware prototype is designed and tested to demonstrate the feasibilities of the proposed rectifier. An input power factor of more than 0.97, peak efficiency of 95.1%, and an output voltage ripple of less than 4.3% across a wide load range have been experimentally obtained.