Single-gate Devices Research Articles

Trade-off analysis between gm/ID and fT of GNR-FETs with single-gate and double-gate device structure

This study examines the operational parameters of field-effect transistors (FETs) using single-gate (SG) and double-gate (DG) graphene nanoribbons (GNRs) within the analog/RF domain. A detailed exploration is conducted through an atomistic pz orbital model, derived from the Hamiltonian of graphene nanoribbons, employing the nonequilibrium Green’s function formalism (NEGF) for analysis. The atomic characteristics of the GNRFETs channel are accurately described by utilizing a tight-binding Hamiltonian with an atomistic pz orbital basis set. The primary focus of the analysis revolves around essential analog/RF parameters such as transconductance, transconductance generation factor (TGF), output resistance, early voltage, intrinsic gain, gate capacitance, cut-off frequency, and transit time. Furthermore, the study assesses the gain frequency product (GFP), transfer frequency product (TFP), and gain transfer frequency product (GTFP) to evaluate the balance between transistor efficiency, gain, and cut-off frequency. The research outcomes indicate that double-gate GNRFETs exhibit superior analog/RF performance in comparison to their single-gate counterparts. However, both types of devices demonstrate cut-off frequencies in the gigahertz range. The extensive data presented in this study provides valuable insights into the characteristics of SG and DG GNRFETs, particularly in terms of the figure-of-merit (FoM) for analog/RF performance, offering a comprehensive analysis of the trade-offs in analog applications. In addition, the analysis has been extended be performing a high-performance hybrid 6T static random-access memory (SRAM) to get the impact in their circuit level variation as well as improvement in their circuit performance.

On the double channel engineering of dual gate AlGaN/GaN HEMTs for heavy ion sensing applications

This work investigates the influence of Single Event Transient (SET) effect on Double Channel Dual Gate (DC-DG) AlGaN/GaN HEMT using TCAD simulations. Both Single Channel (SC) and Double Channel HEMT have been calibrated with reported experimental results and further extended by introducing a second gate in the structures to analyze its sensitivity towards heavy ion strike. The effective gate length has been optimized in such a way that the saturation currents and threshold voltage of dual gate devices is similar to that of the single gate devices. The DC-DG HEMT improves the heavy ion sensitivity, thus making it a more viable device for sensing application (mainly radiation). Different biases and gate materials have been used to observe the influence of SET on the DC-DG AlGaN/GaN HEMT. Further, the impact of the graded AlGaN barrier on the device current as well as on the sensitivity of the DC-DG HEMT towards SET is studied. To ascertain the performance of DC-DG HEMT for dosimeter applications, its sensitivity toward heavy ion impact in switched mode is monitored. Investigation reveals that the device current returns to its original order of magnitude after every ion impact, and therefore can be effectively used as a dosimeter.

Dual-gate manipulation of a HfZrOx-based MoS2 field-effect transistor towards enhanced neural network applications.

Artificial neural networks (ANNs) have strong learning and computing capabilities, and alleviate the problem of high power consumption of traditional von Neumann architectures, providing a solid basis for advanced image recognition, information processing, and low-power detection. Recently, a two-dimensional (2D) MoS2 field-effect transistor (FET) integrating a Zr-doped HfO2 (HZO) ferroelectric layer has shown potential for both logic and memory applications with low power consumption, which is promising for parallel processing of massive data. However, the long-term potentiation (LTP) characteristics of such devices are usually non-linear, which will affect the replacement of ANN weight values and degrade the ANN recognition rate. Here, we propose a dual-gate-controlled 2D MoS2 FET employing HZO gate stack with a crested symmetric structure to reduce power consumption. Improved nonlinearity of the LTP properties has been achieved through the electrical control of the dual gates. A recognition rate reaching 100% is obtained after 60 training epochs, and is 7.89% higher than that obtained from single-gate devices. Our proposed device structure and experimental results provide an attractive pathway towards high-efficiency data processing and image classification in the advanced artificial intelligence field.

Dual-gated ambipolar oxide synaptic transistor for multistate excitatory and inhibitory responses

Developing tunable and multi-input artificial synaptic devices is a significant step to realize diverse functionalities inspired by a bio-neural network and is essential to advance the development of multifunctional human-like neuromorphic devices. This study developed an artificial synaptic device exhibiting tunable and multi-state excitatory and inhibitory responses by using a dual-gated (DG) ambipolar boron-doped SnO thin-film transistor. We demonstrated dynamic modulation of multi-state potentiation/depression responses in both reconfigurable excitatory and inhibitory modes by the DG operation in a single ambipolar transistor. In comparison with conventional single-gate devices, the DG configuration improved the linearity and the symmetricity of synaptic weight updates in addition to the capability of conduction level tuning. Therefore, the presented DG ambipolar oxide synaptic transistor exhibited distinct advantages in learning-accuracy and energy-efficiency, and high pattern recognition accuracy over 90% and low energy operation of ∼200 pJ per pulse in excitatory and inhibitory responses were achieved. It demonstrates the high potential of the DG ambipolar oxide synaptic transistor for next-generation energy-efficient multi-input neuromorphic devices to emulate diverse functionalities in bio-neural network systems.

A Uni-gate vertical power MOSFET with improved figure of Merits: Design and analysis

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga’s Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp).

Improved breakdown characteristic of AlGaN/GaN HEMTs with a width gradient recessed dual-gate structure

A dual-gate (DG) structure utilizing an integrated width gradient DC gate to balance the high-voltage and output current drop was performed for the fabrication of AlGaN/GaN high-electron-mobility transistor (HEMT). In comparison to the traditional single-gate devices, the DG HEMTs combine significantly allowable breakdown voltage behaviour with low gate leakage current and a positive shift threshold voltage, delivering one order of magnitude reduction in leakage current and a 36% improvement in maximum drain bias. The evaluated S parameters substantially exhibit a high power gain potential for DG devices due to the presence of DC gate.

Analog Circuits Using Double-Gate Multilayer MoS2 Field-Effect Transistor for Sensor Applications

The advantages of novel double-gate (DG) multilayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors for analog circuit applications are presented. Such components are shown to be especially useful in signal-conditioning circuits in sensor instrumentation systems. The nearly symmetric DG device architecture can be exploited in the design of analog front-end circuits to mitigate the effect of flicker (1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> ) noise. Quantum mechanical calculations validated by comparisons with experimental data indicate that with active semiconductor layer thickness >2 monolayers (MLs), the sheet carrier density per gate is increased relative to single gate field-effect transistors (FETs) resulting in a lower noise figure. Calculated normalized noise spectral power densities for the single and DG thin-film transistors (TFTs) at the same gate bias clearly show that the DG devices have lower noise than the single gate devices. In sensors for low-frequency signals such as bio-signals, DG transistors allow convenient direct coupling of the signal through one gate, with the other gate available for mixing with a high-frequency signal and/or applying bias voltages without requiring large capacitors. Such circuits are well-suited for use with silicon CMOS technology using back-end-of-the-line (BEOL) fabrication methods.

Analytical modelling for surface potential of dual material gate overlapped-on-drain TFET(DM-DMG-TFET) for label-free biosensing application

This article presented the first-ever 2D analytical model for the surface potential of dual material gate overlapped-on-drain TFET (DMG-TFET) device for label-free biosensor application using dielectric modulation technique. The use of two different metal work functions for the gate (ϕM1<ϕM2) impacts the device’s surface potential to increase tunneling width at the secondary tunneling junction to enhance the device sensitivity compared to single material gate device. This model takes into account the effect of changing the dielectric constant value, location, and percentage of fill factor of the target biomolecules on the surface potential of the device. The parabolic approximation of surface potential is used for solving the 2D-Poisson’s equation by applying suitable boundary conditions. The analytical surface potential results are verified with the simulation result using the SILVACO Atlas tool.

E-mode All-GaN-Integrated cascode MISHEMT with GaN/InAlGaN/GaN backbarrier for high power switching performance: Simulation study

In this work, simulation-based research work based on a novel All-GaN-Integrated Cascode (AGC) MISHEMT with quaternary layer InyAlxGa1-x-yN as backbarrier has been investigated. The AGC-MISHEMT device consists of series combination of enhancement mode (recessed gate MISHEMT) and depletion-mode (MIS-gate) GaN devices with GaN/InAlGaN/GaN sandwich back barrier (SW-BB). TCAD simulations indicate that AGC-MISHEMTs with sandwich back barrier (SW-BB) exhibits simultaneous improvement in terms of drain current density (267 ​mA/mm), high ION/IOFF ratio (108), transconductance-peak (191 ​mS/mm) and breakdown voltage (371 ​V) as compared to AGC-MISHEMT with GaN buffer. The impact of varying mole fractions (x, y), thickness and position of InyAlxGa1-x-yN layer on breakdown voltage has also been examined. Improvement in drain current density up to 40% has been accomplished with increased gate oxide thickness under gate 2 (depletion-mode device) for AGC-MISHEMT with SW-BB. Besides, power switching performance has been compared for AGC-MISHEMT with SW-BB to that of AGC-MISHEMT with GaN buffer and Recessed Single Gate (RSG) MISHEMT for inductive load circuit. Significant reduction in power switching losses (i.e. 43% during turn-ON time and 87% during turn-OFF time) has been observed for AGC-MISHEMT with SW-BB as compared to RSG-MISHEMT. In addition, introduction of quaternary InAlGaN layer in backbarrier for AGC-MISHEMT also results in considerable degradation (∼89%) in power loss when input gate is in OFF-state due to improved ION/IOFF ratio in contrast with recessed single gate device.

Dual metal gate AlGaN/GaN high electron mobility transistors with improved transconductance and reduced short channel effects

AlGaN/GaN high electron mobility transistors with a range of dual metal gate (DMG) lengths have been fabricated and studied. An improvement in transconductance up to 9% has been measured in the DMG devices in comparison to the conventional single metal gate devices. This is attributed to the distribution of the electric field under the gate region as a result of two gate metals. The drain induced barrier lowering is also suppressed using the sub-µm DMG devices, with a drain induced barrier lowering decrease of around 50% due to a potential shielding effect in the two-dimensional electron gas channel.

Performance Investigation of Pentacene Based Organic Double Gate Field Effect Transistor and its Application as an Ultrasensitive Biosensor

In this paper, the electrical performance of double gate organic field effect transistor (DG-OFET) are thoroughly investigated and feasibility of the device as an efficient biosensor is comprehensively assessed. The introduced device provides better gate control over the channel, yielding better charge injection properties from source to channel and providing higher on-state current in comparison with single gate devices. The susceptibility of fundamental electrical parameters with respect to the variation of design parameters is thoroughly calculated. In particular, standard deviation and average value of main electrical parameters signify that metal gate workfunction, channel thickness and gate oxide thickness are fundamental design measures that may modify the device efficiency. The insensitivity of off-state current to the change of channel length and drain bias confirms feasibility of the device in nanoscale regime. Next, a nano cavity is embedded in the gate insulator region for accumulation of biomolecules. The immobilization of molecules with different dielectric constants in the gate insulator hollow alters the gate capacitance and results in the drain current deviation with respect to the air- filled cavity condition. It is shown that by the occupancy of whole volume of the nanogap, a maximum range of on-state current variation can be achieved.

Double-Gate Two-Step Source/Drain Poly-Si Thin-Film Transistor

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device.

3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET * * Project supported by the Ministry of Electronics and Information Technology (MEITy), Govt. of India under its Visvesvaraya PhD Scheme (PhD-MLA/4(55)/2015-16).

The evolution of the traditional metal oxide semiconductor field effect transistor (MOSFET) from planar single gate devices into 3D multiple gates has led to higher package density and high current drive. However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects (SCEs). In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented. The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model. The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.

Suppression of Short-channel Effects by Double-gate Double-channel Device Design in Normally-off AlGaN/GaN MIS-HEMTs

ABSTRACT In this work, we have performed numerical simulations of normally-off AlGaN/GaN recessed Metal–Insulator-Semiconductor or MIS-HEMTs. A double-gate double-channel device design is proposed and analyzed using calibrated TCAD models. The dual-gate geometry is shown to provide an enhanced gate control over the double-channel, thereby suppressing the short-channel effects. The proposed device exhibits 72-mV/decade subthreshold slope, which is 50% improvement compared to the single-gate single-channel device with 3 µm gate length. Both the double-gate double-channel and single-gate single-channel structures are compared for their ability to counter short-channel effects in aggressively scaled MIS-HEMT devices. It is shown that, double-gate design is superior to single-gate single-channel device with 80% improvement in drain-induced barrier lowering at sub-micrometer gate lengths.

Charge Carrier Distribution in Low-Voltage Dual-Gate Organic Thin-Film Transistors

Dual-gate organic thin-film transistors (DGOTFTs), which exhibit better electrical properties, in terms of on-current and subthreshold slope than those of single-gate organic thin-film transistors (OTFTs) are promising devices for high-performance and robust organic electronics. Electrical behaviors of high-voltage (&gt;10 V) DGOTFTs have been studied: however, the performance analysis in low-voltage DGOTFTs has not been reported because fabrication of low-voltage DGOTFTs is generally challenging. In this study, we successfully fabricated low-voltage (&lt;5 V) DGOTFTs by employing thin parylene film as gate dielectrics and visualized the charge carrier distributions in low-voltage DGOTFTs by a simulation that is based on finite element method (FEM). The simulation results indicated that the dual-gate system produces a dual-channel and has excellent control of charge carrier density in the organic semiconducting layer, which leads to the better switching characteristics than the single-gate devices.

Improvement of Subthreshold Characteristic of Gate-Recessed AlGaN/GaN Transistors by Using Dual-Gate Structure

The subthreshold characteristic of gate-recessed high-electron-mobility transistors (HEMTs) using dual-gate (DG) architectures is systematically studied. The recessed DG structure can effectively shift the threshold voltage ( ${V}_{\text {th}}$ ) in the positive direction. Different from the complex function expression between ${V}_{\text {th}}$ and AlGaN thickness ( $\text{t}_{b}$ ) in the recessed single-gate (SG) device, the variation of $\text{V}_{\text {th}}$ with ${t}_{b}$ is monotonic in the recessed DG devices. Recessed DG device exhibits a low off-state leakage current of $\sim {3}\times {10}^{{-10}}$ A/mm and gate induced drain leakage is effectively improved. A higher $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ range of recessed DG devices broadens about 2 times and provide a wider range of ${t}_{b}$ than that of recessed SG devices. The DG structure has a stronger modulation effect on drain–source resistance ( ${R}_{\text {ds}}$ ) and gate–drain resistance ( ${R}_{\text {gd}}$ ) than the SG devices. A lower subthreshold swing (SS) of ~100 mV/dec is obtained by recessed DG design. Due to the second gate inducing the lateral extension of depletion region between the first gate and drain, the off-state leakage and first gate reverse leakage have been significantly improved. Therefore, the recessed DG architecture design can effectively improve the fluctuation of SS and off-state current versus the different AlGaN barrier thickness.

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe2 /WSe2 van der Waals heterostructures with SnSe2 as the p-layer and WSe2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~104 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec-1 for exceeding two decades of drain current with a minimum of 37 mV dec-1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The ION /IOFF ratio of the transfer characteristics is >106 , accompanying a high ON current >10-5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices.

Ultra-low power FinFET-based domino circuits

ABSTRACTAggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.

ELLIPTICAL GATE MOSFETS A MODELING APPROACH

The demand for higher current drives, better short channel characteristics has led to the evolution of multiple gate mosfets from classical single gate devices. Silicon gate all around mosfets(GAA) offers maximum gate control over the channel which makes them an excellent choice among non classical MOS devises. However GAA mosfets with circular cross sections are not common in real fabrication. Elliptical Cross sections have been reported. In this paper new modeling approach for elliptical GAA have been investigated, dependence of physical properties of a device on the behavior of multiple gate devices have been discussed.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.