Single-gate Devices Research Articles

Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs

Gate-induced drain leakage (GIDL) current is investigated in single-gate (SG) ultra-thin body field effect transistor (FET), symmetrical double-gate (DG) FinFET, and asymmetrical DG metal oxide semiconductor field effect transistor (MOSFET) devices. Measured reductions in GIDL current for SG and DG thin-body devices are reported for the first time. The thin-body devices exhibit much lower GIDL current than bulk-Si MOSFETs, and the GIDL is found to decrease with decreasing body thickness. These results can be explained by the reduction in transverse electric field at the surface of the drain and the increase in transverse effective mass with decreasing body thickness.

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-μm single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology.

Manufacturability of single and double-gate ultrathin silicon film fully depleted SOI technologies

Of several possible devices that can be used for sub-70 nm node technologies, two are built on ultra thin SOI layers. Scaling of such thin silicon layer SOI devices is constrained by the severe short channel control problem. To alleviate this, double-gate structures have been proposed by Wong et al. (1999), Chang et al. (2000), and Ieong et al. (2000). In this paper, we assess the manufacturability of single-gate (SG) and symmetric double-gate (DG) devices for gate lengths between 15 and 70 nm. Our results show that SG devices are not only manufacturable but also have tighter distributions than DG devices; inverter ring oscillator (RO) stage delays and power consumption are also better for SG devices. Besides gate length we find two additional major sources of variation: silicon thickness and encapsulation width. We show that for an optimized double-gate device with minimized parasitic resistance, CD variations become a dominant factor at 20-nm gate lengths despite superior electrostatic integrity. Also, the work function of metal gates must be controlled to better than /spl plusmn/0.1 eV (3/spl sigma/) to avoid severe manufacturability problems.

Dual-gate AlGaN/GaN modulation-doped field-effect transistors with cut-off frequencies f/sub T/>60 GHz

We demonstrate dual-gate AlGaN/GaN modulation-doped field-effect transistors (MODFETs) with gate-lengths of 0.16 /spl mu/m and 0.35 /spl mu/m for the first and second gates, respectively. The dual-gate device exhibits a current-gain cut-off frequency f/sub T/>60 GHz, and can simultaneously achieve a high breakdown voltage of >+100 V. In comparison to single-gate devices with the same gate length 0.16 /spl mu/m, dual-gate FETs can significantly increase breakdown voltages, largely increasing the maximum allowable drain bias for high power application. The continuous wave (CW) output power is in excess of 3.5 W/mm at 8.2 GHz. The corresponding large-signal gain is 12 dB and the power added efficiency is 45%. The dual-gate device with different gate lengths shows the capability of providing simultaneous high cut-off frequencies, and high breakdown voltages for broadband power amplifiers.

An experimental analysis of the dual gate emitter switched thyristor (DG-EST)

In recent years, various dual MOS gated thyristor structures have been proposed to improve the three pronged trade-off of forward voltage drop, turn-off time and forward biased safe operating area when compared to single gate devices. The dual gate emitter switched thyristor (DG-EST), with its unique thyristor current partitioning mechanism, has been reported to posses superior characteristics when compared to conventional single gate ESTs. In this paper, a detailed study of the device physics of operation of the DG-EST is presented, supported by two dimensional numerical simulations. Effects of variations in the floating emitter length, lifetime in the drift region and temperature on the forward voltage drop are experimentally observed. An analytical model predicting the maximum controllable current density ( J MCC) of the DG-EST is reported and confirmed through experimental measurements. The DG-EST is found to have a superior trade-off curve of on-state voltage drop versus turn-off time when compared to the conventional emitter switched thyristor (C-EST).

An accurate dual-gate HFET nonlinear model for millimeter-wave MMIC design

An accurate nonlinear model for dual-gate HFETs is presented in this paper. Because of the complexity of the global equivalent circuit, the dual-gate transistor is modeled as two single-gate devices in cascode configuration. A good agreement between the measured and simulated performance is obtained, and its validity is proved as it was used for the design of an MMIC mixer at V-band. © 1998 John Wiley & Sons, Inc. Int J RF and Microwave CAE 8: 315–320, 1998.

A non-local impact ionization/lattice temperature model for VLSI double-gate ultrathin SOI NMOS devices

This paper presents an analytical drain current model for VLSI double-gate ultrathin SOI NMOS devices considering both the nonlocal impact ionization effect and the lattice temperature effect. Supported by the experimental data, the analytical model predicts that the double-gate SOI NMOS device has a more obvious nonlocal impact ionization effect and a higher lattice thermal effect as compared to the single-gate device.

The effect of traps at the free surface of GaAs field effect transistors

In a GaAs field effect transistor there are ungated sections of the channel between the gate and the source/drain. The static characteristics and the transients which occur in various parameters after a change in the bias voltages can be shown to be affected by the surface potential in this region. A model is proposed for these effects which involves a surface region with lower effective energy gap. The gate current leakage characteristics and conductance deep level transient spectroscopy measurements on single and dual gate devices are consistent with this model.

Electrooptic characterization of modulation-doped field-effect transistors with monolithically-integrated test fixtures

The authors report on the fabrication and electrooptic measurement of modulation-dopted field-effect transistors (MODFETs) monolithically integrated with coplanar stripline fixtures incorporating photoconductive switches. Both lattice-matched devices on InP substrates and pseudomorphic devices on GaAs substrates, as well as two different gate access structures have been characterized. In comparing two devices with identical gate access structures, one finds that the delay time of the pseudomorphic device is almost twice as long as that of the lattice-matched device. Surprisingly, the switching times (drain output risetimes) of the two devices are comparable. One also sees that the gate access structure significantly affects the switching in two lattice-matched devices: the switching times for double-gate and single-gate contact devices are 4.2 and 5.2 ps, respectively. In this case, however, no difference was seen in the delay times. These results show that, for the present devices, the switching and delay times are dominated by different mechanisms.

Analysis of the inductive turn-off of double gate MOS controlled thyristors

High voltage inductive turn-off of double gate MOS Controlled Thyristors (MCTs) are analyzed using two-dimensional numerical simulations. Analysis shows that beside the significantly improved maximum controllable current and reduced switching loss, the electric field distribution in these devices has two peaks during inductive turn-off, enabling the maximum turn-off power density to be twice as high as that of the single gate devices. This observation also applies to other double gate bipolar power devices such as double gate Insulated Gate Bipolar Transistors (IGBTs).

Reduction of gate current in AlSb/InAs HEMTs using a dual-gate design

Dual-gate AlSb/InAs HEMTs with 0.4 µm gate lengths have been fabricated, and exhibit a significant reduction in the gate leakage current associated with holes generated by impact ionisation. These HEMTs also have decreased output conductance and increased low frequency unilateral gain compared to single gate devices.

DC and RF characteristics of InAlAs/InGaAs dual-gate TEGFETs

DC and microwave measurements on 0.7 μm single-gate (SG) and dual-gate (DG) In0.52Al0.48As/In0.53Ga0.47As planar doped two-dimensional electron gas field-effect transistors (TEGFETs) are reported. The DG devices show a large increase of the gm to gD ratios, which are as high as 100 at gm = 380mS/mm, compared with 12 at 420mS/mm for the single gate (SG) devices on the same chip, as well as 6dB improvement in the RF power gain compared with their SG counterparts.

Distributed numerical modeling of dual-gate GaAs MESFETs

A one-dimensional, numerical gradual channel model is used to examine the behavior of dual-gate GaAs metal-semiconductor field-effect transistors (MESFETs). Distributed numerical models for dual-gate devices do not incur any significant changes over equivalent single-gate device models. Such distributed numerical models are very useful for examining the regions of operation of each channel and the internal field distributions, and they are applicable when the close proximity of the two gates couples the parameters of the individual channels and invalidates the modeling of the device as two channels in series. The author first derives simplified conditions for saturation and nonsaturation of each gated channel, using as a basis the series connection of two single-gate devices. This load-line approach has been found to be very useful for analyzing switching as well as RF bias conditions. Then the model and method used in a numerical gradual channel analysis of the dual-gate FET are described. The results of the analysis are presented and discussed. >

Single-gate charge-injection device readout modeling and analysis

An in-depth performance analysis of the single-gate charge-injection device (CID) based on a piecewise linear charge-voltage (Q-V) model is presented. Both the voltage- and the current-type readout techniques with sequential access scheme for the linear CID arrays are considered. Heuristic views on CID charge readout efficiency degradation due to depletion loading and lag caused by injection pulse loading are illustrated. Transient and steady-state characteristics of the detector are demonstrated by a step-function response. Performance parameters of the CID array as an infrared sensor are summarized and compared to evaluate the relative merits of each readout scheme.

S-parameter model of dual-gate GaAs MESFET

A simple modelling procedure for the dual-gate MESFET is presented. The model is based on a cascoded connection of two single-gate devices, with each device represented in terms of its s-parameters. These s-parameters are obtained from the overall dual-gate MESFET s-parameters, using accurate deembedding techniques.

Experimental comparisons in the electrical performance of long and ultrashort gate length GaAs MESFET's

Electrical properties of GaAs single-gate and dual-gate MESFET's with gate lengths of 1.2 µm and 0.2 µm have been compared. By reducing the gate length to 0.2 µm, a very high zero-gate-bias drain current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dss</inf> and a large increase in the pinchoff voltage were observed in both single-gate and dual-gate devices, I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dss</inf> in the shorter gate FET was found to be very close to the full channel current. Only a slight improvement in the maximum intrinsic g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> was noted in the 0.2 µm FET's. The knee voltage for the zero-gate-bias curve was larger in the shorter gate FET. At low current levels, soft pinchoff and soft saturation behaviors were observed in the very short gate FET's. A striking feature of the GaAs MESFET is that its output conductance at large drain voltages does not degrade with shorter gate lengths.

Performance and Design of Microwave FET Harmonic Generators

Experimental measurements of the power gain of a 4- to 8-GHz frequency doubler, employing a single-gate GaAs MESFET device and a microstrip circuit, are reported. The measured performance provides design guidelines, and is explained in terms of FET characteristics. In particular, the multiplication gain is largest when the FET is biased near pinchoff.

Dual-gate gallium-arsenide microwave field-effect transistor

Dual-gate gallium-arsenide field-effect transistors have been fabricated which give power gains greater than those which can be obtained from single-gate devices of similar gate length. Unconditionally stable gains in excess of 12 dB at 5 GHz have been measured for these devices.