Single Field Programmable Gate Array Research Articles

FPGA based failure monitoring system for machining processes

To be adapted in an easy and economical manner to several machining processes is a desired characteristic in any proposed tool condition monitoring system so as to detect or avoid failures in machine tools. Many modern rotating machines have a servodriver which may, without sensors, acquire a current signal which is directly related to the cutting forces and then be correlated to the cutting tool conditions. Most of the reported systems are designed to work only in one machining process; yet the novelty of this paper is the fact of presenting a hardware signal processing unit implemented in a single field-programmable gate array (FPGA) for acquisition, conditioning, and basic signal monitoring in several machining processes. The system has been proven in industrial processes as well as in laboratories with satisfactory results in both cases. This model is reconfigurable and scalable so that it may be adapted to diverse conditions as an economical stand-alone unit since it does not require either computers nor microprocessors.

Deep network packet filter design for reconfigurable devices

Most network routers and switches provide some protection against the network attacks. However, the rapidly increasing amount of damages reported over the past few years indicates the urgent need for tougher security. Deep-packet inspection is one of the solutions to capture packets that can not be identified using the traditional methods. It uses a list of signatures to scan the entire content of the packet, providing the means to filter harmful packets out of the network. Since one signature does not depend on the other, the filtering process has a high degree of parallelism. Most software and hardware deep-packet filters that are in use today execute the tasks under Von Neuman architecture. Such architecture can not fully take advantage of the parallelism. For instance, one of the most widely used network intrusion-detection systems, Snort, configured with 845 patterns, running on a dual 1-GHz Pentium III system, can sustain a throughput of only 50 Mbps. The poor performance is because of the fact that the processor is programmed to execute several tasks sequentially instead of simultaneously. We designed scalable deep-packet filters on field-programmable gate arrays (FPGAs) to search for all data-independent patterns simultaneously. With FPGAs, we have the ability to reprogram the filter when there are any changes to the signature set. The smallest full-pattern matcher implementation for the latest Snort NIDS fits in a single 400k Xilinx FPGA (Spartan 3-XC3S400) with a sustained throughput of 1.6 Gbps. Given a larger FPGA, the design can scale linearly to support a greater number of patterns, as well as higher data throughput.

On the Implementation of a Wavelet-based Iterative Learning Controller Using CPLD/FPGA

The realization of a wavelet-based iterative learning controller (WILC) is presented in this paper. To meet the requirements of simplified hardware, fast rapid prototyping and fast up-date cycle, a wavelet-based iterative learning control system is implemented on a single FPGA (Field Programmable Gate Array). There are three modules in this FPGA-based system, they are a feedback module, a discrete wavelet transform (DWT) module and an inverse discrete wavelet transform (IDWT) module. An external static random access memory (SRAM) is also employed to store the learning control signal processed by wavelet transform before updating the feedback control signal. To verify its effectiveness, a belt-driven ink-jet printer is adopted as the control target and a much improved speed-tracking performance is observed from the experimental verification. With the help of the learning process, the ink-jet printer needs no calibration during continuous operation and the velocity of the printer-head can be steadily running at 24 inch/sec.

Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

The authors present a novel virtual reconfigurable architecture (VRA) for realising real-world applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays (FPGAs). The phenotype representation of the proposed evolvable system is based on a two-dimensional function element (FE) network. Compared with the traditional Cartesian genetic programming, the proposed approach includes more connection restrictions in the FE network to reduce genotype length. Another innovative feature of the VRA is that the whole evolvable system, which consists of an evolutionary algorithm unit, a fitness value calculation unit and an FE array unit, can be realised on a single FPGA. On this work, a custom Xilinx Virtex xcv2000E FPGA, which is fitted in the Celoxica RC1000 Peripheral Component Interconnect (PCI) board is utilised as the hardware platform. The main motive of the research is to design a general, flexible evolvable system with powerful computation ability to achieve intrinsic evolution. As examples, the proposed evolvable system is devoted to evolve two real-world applications: a character recogniser and an image operator by using gate level evolution and function level evolution, respectively. The experimental results show that the VRA can bring higher computational ability and more flexibility than traditional approach to intrinsic EHW.

A Stochastic-Based FPGA Controller for an Induction Motor Drive With Integrated Neural Network Algorithms

This paper applies stochastic theory to the design and implementation of field-oriented control of an induction motor drive using a single field-programmable gate array (FPGA) device and integrated neural network (NN) algorithms. Normally, NNs are characterized as heavily parallel calculation algorithms that employ enormous computational resources and are less useful for economical digital hardware implementations. A stochastic NN structure is proposed in this paper for an FPGA implementation of a feedforward NN to estimate the feedback signals in an induction motor drive. The stochastic arithmetic simplifies the computational elements of the NN and significantly reduces the number of logic gates required for the proposed NN estimator. A new stochastic proportional-integral speed controller is also developed with antiwindup functionality. Compared with conventional digital controls for motor drives, the proposed stochastic-based algorithm enhances the arithmetic operations of the FPGA, saves digital resources, and permits the NN algorithms and classical control algorithms to be easily interfaced and implemented on a single low-complexity, inexpensive FPGA. The algorithm has been realized using a single FPGA XC3S400 from Xilinx, Inc. A hardware-in-the-loop (HIL) test platform using a Real Time Digital Simulator is built in the laboratory. The HIL experimental results are provided to verify the proposed FPGA controller.

Optical Doppler tomography based on a field programmable gate array

We report the design of and results obtained by using a field programmable gate array (FPGA) to digitally process optical Doppler tomography signals. The processor fits into the analog signal path in an existing optical coherence tomography setup. We demonstrate both Doppler frequency and envelope extraction using the Hilbert transform, all in a single FPGA. An FPGA implementation has certain advantages over general purpose digital signal processor (DSP) due to the fact that the processing elements operate in parallel as opposed to the DSP, which is primarily a sequential processor.

A Link-Layer Slave Device Design of the MVB-TCN Bus (IEC 61375 and IEEE 1473-T)

The train communication network standard was approved in 1999 by the International Electrotechnical Commission (IEC) and the IEEE to warrant train and equipment interoperability. However, we have not found any published work presenting a top-down device design that is compliant with this standard. None of the found publications deals with the real-time protocols of the design nor resolves the many open points left in it. The link-layer design that is presented here implements the full set of specifications of the IEC 61375-1 standard (also named the IEEE 1473-T standard) that is related to the slave devices for the multifunction vehicle bus (MVB), including all of its real-time protocols, procedures, and free options. It is the first step to obtaining a true system-on-chip, including all the layers of any MVB device, as stated by the standard. Our proposal is based on a concurrent, easily parameterized and reconfigurable, top-down design procedure that is implemented in a single field-programmable gate array plus a very simple embedded application processor. The performance of our design is only limited by the standard constraints themselves, which is restricted neither by its proposed implementation nor by our design criteria.

An FPGA-Based Doppler Processor for a Spaceborne Precipitation Radar

Abstract Measurement of precipitation Doppler velocity by spaceborne radar is complicated by the large velocity of the satellite platform. Even if successive pulses are well correlated, the velocity measurement may be biased if the precipitation target does not uniformly fill the radar footprint. It has been previously shown that the bias in such situations can be reduced if full spectral processing is used. The authors present a processor based on field-programmable gate array (FPGA) technology that can be used for spectral processing of data acquired by future spaceborne precipitation radars. The requirements for and design of the Doppler processor are addressed. Simulation and laboratory test results show that the processor can meet real-time constraints while easily fitting in a single FPGA.

An FPGA-Based Optical Transmitter Design Using Real-Time DSP for Advanced Signal Formats and Electronic Predistortion

Advances in the performance and flexibility of future optical networks will be brought about through the use of high-speed digital signal processing (DSP) for the generation of advanced optical signal formats and the compensation of transmission impairments. The use of field-programmable gate arrays (FPGAs) to implement experimental transceivers employing novel DSP techniques is attractive, as they are of low cost and are reprogrammable. In this paper, the design of a reprogrammable FPGA-based 10-Gb/s optical transmitter using real-time DSP is described and assessed through simulation. Using a single Xilinx Virtex-4 FPGA, digital filtering based on lookup tables with up to 12-bit addressing could be implemented. We also present, for the first time, a simulation technique using industry-standard digital design simulation tools (mentor graphics modelsim) in combination with a simulation of analog microwave components, optical transmission, and bit-error-rate estimation to assess the performance of the full transmission system. This simulation technique is used to demonstrate 10-Gb/s transmission over 550 km of standard single-mode fiber (SSMF) using electronic predistortion (EPD) and the generation of optical single sideband signals. A proof-of-principle experiment is described in which a single 10.7-Gb/s Mach-Zehnder modulator drive signal with 4-bit amplitude resolution and 1-sample/bit temporal resolution was generated. This was used as the input to Monte Carlo simulations to assess EPD transmission performance over SSMF links of up to 640 km.

FPGA realization of adaptive speed control IC for PMSM drive

This paper presents an adaptive speed control IC for use in a PMSM (Permanent Magnet Synchronous Motor) drive based on FPGA (Field Programmable Gate Array) technology. Firstly, PMSM is mathematics modelled and the vector control scheme is introduced in the current loop of the PMSM drive. Secondly, to increase the performance of the PMSM drive, an AFC (Adaptive Fuzzy Controller) constructed by a fuzzy basis function and a parameter adjustable mechanism is derived and applied to the speed loop of a PMSM drive to cope with the effect of the system dynamic uncertainty and external load. Thirdly, a proposed adaptive speed control IC based on the FPGA is employed to realize the aforementioned current vector controller and adaptive speed controller of PMSM drive. In addition, a FSMD (Finite State Machine with a Datapath) is presented to model the overall AFC algorithm. As a result, a fully digital controller, including the AFC, the current vector scheme, SVPWM (Space Vector Pulse Width Modulation) generation, coordinate transformation and QEP (Quadrature Encoder Pulse) detection, for PMSM drive can be realized within a single FPGA chip. Finally, an experimental system is set up and some experimental results are demonstrated.

Implementing Spiking Neural Networks for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach

In this paper, we present two versions of a hardware processing architecture for modeling large networks of leaky-integrate-and-fire (LIF) neurons; the second version provides performance enhancing features relative to the first. Both versions of the architecture use fixed-point arithmetic and have been implemented using a single field-programmable gate array (FPGA). They have successfully simulated networks of over 1000 neurons configured using biologically plausible models of mammalian neural systems. The neuroprocessor has been designed to be employed primarily for use on mobile robotic vehicles, allowing bio-inspired neural processing models to be integrated directly into real-world control environments. When a neuroprocessor has been designed to act as part of the closed-loop system of a feedback controller, it is imperative to maintain strict real-time performance at all times, in order to maintain integrity of the control system. This resulted in the reevaluation of some of the architectural features of existing hardware for biologically plausible neural networks (NNs). In addition, we describe a development system for rapidly porting an underlying model (based on floating-point arithmetic) to the fixed-point representation of the FPGA-based neuroprocessor, thereby allowing validation of the hardware architecture. The developmental system environment facilitates the cooperation of computational neuroscientists and engineers working on embodied (robotic) systems with neural controllers, as demonstrated by our own experience on the Whiskerbot project, in which we developed models of the rodent whisker sensory system.

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.

Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization

This paper presents a hardware implementation of multilayer feedforward neural networks (NN) using reconfigurable field-programmable gate arrays (FPGAs). Despite improvements in FPGA densities, the numerous multipliers in an NN limit the size of the network that can be implemented using a single FPGA, thus making NN applications not viable commercially. The proposed implementation is aimed at reducing resource requirement, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The sequential processing of the layers in an NN has been exploited in this paper to implement large NNs using a method of layer multiplexing. Instead of realizing a complete network, only the single largest layer is implemented. The same layer behaves as different layers with the help of a control block. The control block ensures proper functioning by assigning the appropriate inputs, weights, biases, and excitation function of the layer that is currently being computed. Multilayer networks have been implemented using Xilinx FPGA "XCV400hq240". The concept used is shown to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is proposed to make NN applications viable in terms of cost and speed for online applications. An NN-based flux estimator is implemented in FPGA and the results obtained are presented.

Hardware Implementation of a Real-Time Neural Network Controller With a DSP and an FPGA for Nonlinear Systems

In this paper, we implement the intelligent neural network controller hardware with a field programmable gate array (FPGA)-based general purpose chip and a digital signal processing (DSP) board to solve nonlinear system control problems. The designed intelligent control hardware can perform real-time control of the backpropagation learning algorithm of a neural network. The basic proportional-integral-derivative (PID) control algorithms are implemented in an FPGA chip and a neural network controller is implemented in a DSP board. By using a high capacity of an FPGA chip, the additional hardware such as an encoder counter and a pulsewidth modulation (PWM) generator is implemented in a single FPGA chip. As a result, the controller becomes cost effective. It was tested for controlling nonlinear systems such as a robot finger and an inverted pendulum on a moving cart to show performance of the controller

Single sensor current control of permanent magnet synchronous motor using field programmable gate array

An innovative current control scheme for a permanent magnet synchronous motor using a single current sensor placed at a low potential, in the DC return line of the inverter is proposed. The feedback mechanism employs a digital asymptotic sinusoidal curve-fitting observer implemented in a single field programmable gate array chip. The observer, activated by firing pulses, reconstructs the three-phase feedback signals. The asymptotic observer does not require the parameters of the motor or the load and it is robust under dynamic conditions. The development of the algorithm, implementation and experimental verification of the proposed control scheme are presented in detail.

Performance evaluation of an FPGA controlled soft switched inverter

A field programmable gate array (FPGA) based controller is proposed for a dc link series resonant inverter. The basic operation of the zero current switching inverter is briefly described. A strategy of decoupling the control of the dc link current from the load current is identified and referred as decoupled current control (DCC). The use of gate-controlled devices like metal–oxide–semiconductor field-effect transistor/insulated gate bipolar transistor/MOS-controlled thyristor permits a higher resonance frequency at the link of the inverter. The increased frequency enables the application of pulse density modulation technique with a bang–bang controller to synthesise and control the wave-shapes of current and voltage of the inverter. The DCC strategy eliminates the conventional analogue controller. A digital sequence controller has been designed using the state machine technique for the reliable operation of the inverter. The digital design is implemented on a single chip FPGA. To verify the proposed control strategy and the FPGA controller, a prototype has been built and tested. The test results show that a sinusoidal inverter output voltage is maintained with total harmonic distortion less than 5% and a regulation of about 1% from no-load to full-load, including non-linear and transient loads. The performance of the inverter with the FPGA controller is promising and attractive for uninterrupted power supply applications.

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

FPGAs (Field-Programmable Gate Arrays) have been widely used as coprocessors to boost the performance of data-intensive applications [1], [2]. However, there are several challenges to further boost FPGA performance: the communication overhead between the host workstation and the FPGAs can be substantial; large-scale applications cannot fit in a single FPGA because of its limited capacity; mapping an application algorithm to FPGAs still remains a daunting job in configurable system design. To circumvent these problems, we propose in this paper the FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Pyramidal Instruction Set Architecture (PISA). PISA comprises high-level instructions implemented as FPGA functions of coarse-grain SIMD (Single-Instruction, Multiple-Data) tasks to facilitate ease of program development, code portability across different H-SIMD implementations and high performance. We assume a multi-FPGA board where each FPGA is configured as a separate SIMD machine. Multiple FPGA chips can work in unison at a higher SIMD level, if needed, controlled by the host. Additionally, by using a memory switching scheme and the high-level PISA to partition applications into coarse-grain tasks, host-FPGA communication overheads can be hidden. We enlist the two-dimensional Fast Fourier Transform (2D FFT) to test the effectiveness of H-SIMD. The test results show sustained high performance for this problem. The H-SIMD machine even outperforms a Xeon processor for this problem.

SAD computation based on online arithmetic for motion estimation

Block-based motion estimation is one of the critical tasks in today's video compression standards such as H.26x, MPEG-1, -2 and -4. Most of the block-based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference blocks. In this paper, an field-programmable gate-array (FPGA) design is proposed for rapidly computing the minimum SAD. Two goals are achieved due to the use of online arithmetic (OLA): it is possible to implement a full 16×16 macroblock SAD in a single FPGA device; and it allows us to speed up computation by early termination of the SAD calculation when the candidate involved is bigger than the current reference SAD. Reconfigurable devices enable us to change 8×8 or 16×16 pixels per block quickly and easily. For a 16×16 SAD unit 1945 look-up tables (LUTs) are required at 425 MHz. A comparison with other related works is provided.

A Reconfigurable FPGA System for Parallel Independent Component Analysis

A run-time reconfigurable field programmable gate array (FPGA) system is presented for the implementation of the parallel independent component analysis (ICA) algorithm. In this work, we investigate design challenges caused by the capacity constraints of single FPGA. Using the reconfigurability of FPGA, we show how to manipulate the FPGA-based system and execute processes for the parallel ICA (pICA) algorithm. During the implementation procedure, pICA is first partitioned into three temporally independent function blocks, each of which is synthesized by using several ICA-related reconfigurable components (RCs) that are developed for reuse and retargeting purposes. All blocks are then integrated into a design and development environment for performing tasks such as FPGA optimization, placement, and routing. With partitioning and reconfiguration, the proposed reconfigurable FPGA system overcomes the capacity constraints for the pICA implementation on embedded systems. We demonstrate the effectiveness of this implementation on real images with large throughput for dimensionality reduction in hyperspectral image (HSI) analysis.

Mapping a Sensor Interface and a Reconfigurable Communication System to an FPGA Core

In this short communication, we present a novel approach for integrating a standard sensor interface and a reconfigurable wireless data communication channel on a single Field Programmable Gate Array (FPGA) chip. In a traditional wireless sensor device, sensor and communication electronics are built as separate components and their integration consists of designing a board to accommodate multiple integrated circuits (ICs). In contrast, the FPGA core allows us to put a standard I²C sensor interface, embedded Digital Signal Processing (DSP) algorithms for Software-Defined Radio (SDR), and a microprocessor control system on a singlechip reconfigurable device. In our experimental FPGA-based sensor platform, the I²C interface is used both to receive data from the temperature sensor and to control the analog Radio Frequency (RF) transceiver board. Amplitude Shift Keying (ASK) modulation and demodulation are implemented using DSP techniques within an SDR framework, and the microprocessor system is used to read sensor data and control various components. The prototype design was deployed on a Nallatech development board containing a Xilinx Virtex 2V3000 FPGA chip and was successfully tested with Dallas Semiconductor DS1721 digital temperature sensor. One instance of the prototype transmitted the temperature red by the sensor while second instance acted upon the received over the air temperature readings by turning LED on or off.