Single Field Programmable Gate Array Research Articles

Dual priority dynamic scheduling algorithm based on multi-FPGA

When single Field-Programmable Gate Array(FPGA) deals with the huge amounts of data in high-speed network,low efficiency problem occurs.According to dual priority schedule algorithm for multi-processor and high-speed data acquisition and processing model based on multi-FPGA,a dual priority dynamic scheduling algorithm was proposed based on multi-FPGA.For strong real-time periodic tasks set in low priority queue,the Earliest Deadline Critical Laxity(EDCL) scheduling algorithm was given to determine the priority of task according to the degree of relaxation of the tasks.If the task was not finished when the promotion time was up,it would be promoted to high priority queue.For soft real-time periodic tasks,an algorithm was put forward to assign the tasks to middle priority queue and schedule them by delaying the deadline of tasks to dynamic blur threshold.The experimental results show that the proposed algorithms can well schedule strong real-time periodic tasks and guarantee the priority execution of important tasks,and it can also reduce miss rate of soft real-time periodic tasks caused by preemption.

A new realization of time-to-digital converters based on FPGA internal routing resources

Time-to-digital converters (TDC) implemented in a single field-programmable gate array (FPGA) chip which overcome the difficulties found in other FPGA-based TDCs are proposed in this paper. Emphasis is placed on the construction of two delay lines with a good delay consistency, as well as a minimum delay difference by which the measurement resolution can be improved and measurement error can be reduced. A modified vernier delay line structure is introduced which abandoned special delay elements and directly used FPGA internal routing resources to generate the cell delay. To get a good consistency for the system, manual placement and manual routing are used to standardize the delays. The resolution of the system is 9 ps and the standard deviation is less than 1 least significant bit (LSB) within the whole measurement range. The corrected differential nonlinearity is as low as 0.11 LSB. Experiments showed that the proposed system features high accuracy, low cost, and high stability.

FPGA-Based Fast Detection With Reduced Sensor Count for a Fault-Tolerant Three-Phase Converter

Fast fault detection (FD) and reconfiguration is necessary for fault tolerant power electronic converters in safety critical applications to prevent further damage and to make the continuity of service possible. The aim of this study is to minimize the number of the used additional voltage sensors in a fault tolerant three-phase converter. In this paper, first a practical implementation of a very fast FD scheme with reduced sensor number is discussed. Then, an optimization in this scheme is also presented to decrease the detection time. For FD, special time and voltage criterion are applied to observe the error in the estimated phase-to-phase voltages for a specific period of time. The proposed optimization is based on the fact that following a detectable fault, two line-to-line voltages will deviate from their respective estimated values. Fault detection is studied for a three-leg two-level fault tolerant converter. Control and FD systems are implemented on a single field-programmable gate array. First, hardware in the loop experiments are carried out to evaluate the implemented schemes. Then, fully experimental tests are performed. The results confirm good performance of the proposed detection schemes, the digital controller and the fault tolerant structure. It is shown that such methods can detect and locate a fault in a few tens of microseconds. In certain cases the optimized scheme can be faster up to 50%, and in the other cases they have the same detection time.

Real-time lane departure warning system based on a single FPGA

Abstract Abstract This paper presents a camera-based lane departure warning system implemented on a field programmable gate array (FPGA) device. The system is used as a driver assistance system, which effectively prevents accidents given that it is endowed with the advantages of FPGA technology, including high performance for digital image processing applications, compactness, and low cost. The main contributions of this work are threefold. (1) An improved vanishing point-based steerable filter is introduced and implemented on an FPGA device. Using the vanishing point to guide the orientation at each pixel, this algorithm works well in complex environments. (2) An improved vanishing point-based parallel Hough transform is proposed. Unlike the traditional Hough transform, our improved version moves the coordinate origin to the estimated vanishing point to reduce storage requirements and enhance detection capability. (3) A prototype based on the FPGA is developed. With improvements in the vanishing point-based steerable filter and vanishing point-based parallel Hough transform, the prototype can be used in complex weather and lighting conditions. Experiments conducted on an evaluation platform and on actual roads illustrate the effective performance of the proposed system.

Fault-Tolerant Five-Leg Converter Topology With FPGA-Based Reconfigurable Control

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable controller, and fault detection scheme. For experimental tests, the control and the fault detection and reconfiguration schemes are implemented on a single field-programmable gate array (FPGA) chip. Experimental and simulation results show the effectiveness of the proposed fault-tolerant topology and its FPGA-based control.

Realization of a Motion Control System for Wafer-Handling Robot Using SoPC Technology

The novel FPGA (Field Programmable Gate Arrays) can embed a processor to be an SoPC (System-on-a-Programmable-Chip) environment which allows user to design the applications by mixing hardware and software. Therefore, a motion control system of wafer-handling robot based on the SoPC technology is presented in this paper. In FPGA, it is consists of two modules. The first module is Nios II processor which is used to realize the motion trajectory planning and three-axis position/speed controllers by software. The program developed in Nios II processor uses C language. The second module is presented to implement three-axis current vector controllers by hardware, and VHDL (VHSIC Hardware Description Language) is applied to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as three current vector controllers, three position/speed controller and one trajectory planning are all can implemented by a single FPGA chip. Finally, an experimental system constructed by an FPGA experimental board, one three-DOF wafer-handling robot, and three inverters is set up to demonstrate the correctness and effectiveness of the proposed SoPC-based motion control system of wafer-handling robot.

Mapping Floating-Point Kernels onto High Performance Reconfigurable Computers

Contemporary field programmable gate arrays (FPGAs) combine the fine-grained design capability of the traditional lookup table with the speed of medium-scale and large-scale logic components such as RAM blocks or DSP blocks to provide for significant computational capability from a single FPGA. High performance reconfigurable computers, which typically use FPGAs as computational elements, have been commercially used to accelerate computational kernels. However, the deep pipelines and extensive parallelism needed for FPGAs to compete with GHz-scale general purpose processors make mapping of floating-point kernels a challenging research area. In this paper, we describe some of the progress that has been made towards solving some of these mapping challenges.

Low-Noise Low-Delay Digital Signal Processor for Resonant Micro Optic Gyro

A low-noise low-delay digital signal processor is constructed on a single field-programmable gate array. An equivalent input noise as low as 3.752 nV/√Hz is demonstrated for the digital signal processor, which can detect an equivalent Sagnac effect of 0.003°/s in a resonant micro optic gyro (RMOG) with a 2.5-cm diameter ring resonator. With the processing time reduced from hundreds of seconds to 1.1 μs , this processor significantly increases the loop gain of the feedback loop and reduces the reciprocal noise in the RMOG. Owing to the fast speed of this processor, the lock-in frequency accuracy is reduced to 0.78 Hz (1σ), which is equivalent to a rotation rate of 0.004°/s. Relationship between this digitalized RMOG output signal and angular rate is obtained from ±0.25°/s to ±400°/s. The standard deviation of the residuals between RMOG output results and linear fit curve is 0.0236°/s.

NeuroFlow: FPGA-based Spiking Neural Network Acceleration with High-level Language Support

Event Abstract Back to Event NeuroFlow: FPGA-based Spiking Neural Network Acceleration with High-level Language Support Kit Cheung1*, Simon R. Schultz2 and Wayne Luk1 1 Imperial College London, Department of Computing, United Kingdom 2 Imperial College London, Department of Bioengineering, United Kingdom Spiking neural networks are a useful tool for cortical modelling and robotic control, but simulating a large network in real-time requires high-performance computers or specially built accelerators. Traditional accelerators for large-scale spiking neural network accelerators developed previously use Graphics Processing Units (GPUs) or Application-Specific Integrated Circuit (ASIC) chips. While ASICs deliver high performance, they lack the flexibility to reconfigure and hence are unable to adapt variation in the design and models employed. On the other hand, GPUs provides a decent speedup over multi-core CPUs and good flexibility, but it lacks scalability to handle larger networks. In this work we present NeuroFlow, a Field Programmable Gate Array (FPGA)-based spiking neural network accelerator consisting of 4 FPGAs. It supports the use of PyNN, a high-level simulator-independent network description language, to configure the hardware. A major novelty of the system is the capability to provide custom hardware configuration based on various simulation requirements, such as precision and time delay. The accelerator is implemented on an off-the-shelf MPC-C500 from Maxeler Technology which employs a streaming architecture in the FPGAs. The accelerator achieves the performance gain primarily by parallelizing the computation of point-neuron models and employing low-level optimization for synaptic data memory access. The accelerator currently supports basic PyNN functions such as spike-timing-dependent plasticity (STDP) and arbitrary postsynaptic current kernels. The system is able to support simulation of network of approximately 800,000 neurons, and achieve a real-time performance of 400,000 neurons for a network firing at 8Hz with random connections. With a single FPGA running at 150MHz, the accelerator delivers a throughput of 1.9 times to 3.5 times the performance of one of the most recent GPU-based accelerators in terms of postsynaptic potential delivery rate (Fidjeland et al., Neuroinformatics, 2012 Dec), subject to the simulated network and the GPU model used. In conclusion, while harnessing low-level customization and fine grained parallelism in FPGA, NeuroFlow is also able to provide the flexibility of a high-level platform such as GPUs and high-performance computers. It provides a promising alternative to accelerate spiking neural network simulations. Figure 1 Figure 2 Acknowledgements The research leading to these results has received funding from European Union Seventh Framework Programme under grant agreement number 287804, 248976 and 257906. The support by the Croucher Foundation, UK EPSRC, HiPEAC NoE, Maxeler University Program, and Xilinx is gratefully acknowledged. Keywords: FPGA, Spiking Neural network, PyNN, Hardware Acceleration, Dataflow Computing Conference: Neuroinformatics 2013, Stockholm, Sweden, 27 Aug - 29 Aug, 2013. Presentation Type: Oral presentation Topic: Neuromorphic engineering Citation: Cheung K, Schultz SR and Luk W (2013). NeuroFlow: FPGA-based Spiking Neural Network Acceleration with High-level Language Support. Front. Neuroinform. Conference Abstract: Neuroinformatics 2013. doi: 10.3389/conf.fninf.2013.09.00095 Copyright: The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers publishing platform as a service to conference organizers and presenters. The copyright in the individual abstracts is owned by the author of each abstract or his/her employer unless otherwise stated. Each abstract, as well as the collection of abstracts, are published under a Creative Commons CC-BY 4.0 (attribution) licence (https://creativecommons.org/licenses/by/4.0/) and may thus be reproduced, translated, adapted and be the subject of derivative works provided the authors and Frontiers are attributed. For Frontiers’ terms and conditions please see https://www.frontiersin.org/legal/terms-and-conditions. Received: 08 Apr 2013; Published Online: 11 Jul 2013. * Correspondence: Mr. Kit Cheung, Imperial College London, Department of Computing, London, United Kingdom, k.cheung11@imperial.ac.uk Login Required This action requires you to be registered with Frontiers and logged in. To register or login click here. Abstract Info Abstract Supplemental Data The Authors in Frontiers Kit Cheung Simon R Schultz Wayne Luk Google Kit Cheung Simon R Schultz Wayne Luk Google Scholar Kit Cheung Simon R Schultz Wayne Luk PubMed Kit Cheung Simon R Schultz Wayne Luk Related Article in Frontiers Google Scholar PubMed Abstract Close Back to top Javascript is disabled. Please enable Javascript in your browser settings in order to see all the content on this page.

Design and Optimization of Flexible and Coding Efficient All-Digital RF Transmitters

All-digital transmitters are getting increased attention due to its closer proximity to the ideal software-defined radio (SDR) transmitter. In this paper we propose a new transmitter architecture that addresses two key limitations of current approaches, namely, the poor coding efficiency and the high quality factor requirements of the RF output reconstruction filter that significantly limit the practical usability and dissemination of these new flexible RF transmitters. The proposed architecture combines a maximum coding efficiency of 79.3% and a signal-to-noise ratio (SNR) of 50 dB, while maintaining the high flexibility inherent to the all-digital transmitters and where the RF output carriers operating in the microwave frequency range are generated inside a single field-programmable gate array (FPGA) device. The obtained results also show the feasibility and potential of using FPGA-based architectures for implementing digital RF transmitters.

A Beam Phase and Energy Measurement Instrument Based on Direct RF Signal IQ Undersampling Technique

A diagnostic instrument being designed to measure the beam phase and energy of the drift tube linac in the proton accelerator of the China Spallation Neutron Source is described, and the characterization of the system is presented. The signals received from fast current transformers are radio-frequency (RF) signals with a frequency of 352.2 MHz and a dynamic range from -30 to 3.5 dBm. The RF signals are converted to orthogonal streams directly with the in- and quadrature-phase undersampling technique based on high-speed high-resolution analog-to-digital (A/D) conversion. To guarantee a high-quality A/D conversion, two different sampling clock circuits are designed with corresponding simulations and tests conducted for comparison. To build a stand-alone instrument with compact architecture, all digital signal processing algorithms are implemented within one single field-programmable gate array; meanwhile, a Nios II embedded system is also integrated in it for data transfer through the Ethernet. This system achieves a phase resolution better than 0.09° over the input signal amplitude range from -41 to 7 dBm, well beyond the 0.5° required.

A Time Domain Reflectometer with 100 ps precision implemented in a cost-effective FPGA for the test of the KLOE-2 Inner Tracker readout anodes

A Time Domain Reflectometer implemented in a single cost-effective Field Programmable Gate Array device is shown to achieve a precision around 100ps. The Time to Digital Converter section of the device is based on a tapped delay line followed by an encoder and shows both Differential and Integral Non-Linearity below one least significant bit. The same Field Programmable Gate Array houses an 8051 8-bits microprocessor, for the control of the pulse signals generation, the acquisition and the first treatment of raw data. Principles of operation, architecture, performance and preliminary trials on the prototype are presented in this paper. As an example of possible application, the proposed circuit has been usefully used to perform the quality control of the micro-strip anodic planes of the Gas Electron Multiplier Inner Tracker of the KLOE-2 experiment.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

Upgrade of the trigger system of CMS

Various parts of the CMS trigger and in particular the Level-1 hardware trigger will be upgraded to cope with increasing luminosity, using more selective trigger conditions at Level 1 and improving the reliability of the system. Many trigger subsystems use FPGAs (Field Programmable Gate Arrays) in the electronics and will benefit from developments in this technology, allowing us to place much more logic into a single FPGA chip, thus reducing the number of chips, electronic boards and interconnections and in this way improving reliability. A number of subsystems plan to switch from the old VME bus to the new microTCA crate standard. Using similar approaches, identical modules and common software wherever possible will reduce costs and manpower requirements and improve the serviceability of the whole trigger system. The computer-farm based High-Level Trigger will not only be extended by using increasing numbers of more powerful PCs but there are also concepts for making it more robust and the software easier to maintain, which will result in better efficiency of the whole system.

Synchronized operation by field programmable gate array based signal controller for the Thomson scattering diagnostic system in KSTAR

The Thomson scattering diagnostic system is successfully installed in the Korea Superconducting Tokamak Advanced Research (KSTAR) facility. We got the electron temperature and electron density data for the first time in 2011, 4th campaign using a field programmable gate array (FPGA) based signal control board. It operates as a signal generator, a detector, a controller, and a time measuring device. This board produces two configurable trigger pulses to operate Nd:YAG laser system and receives a laser beam detection signal from a photodiode detector. It allows a trigger pulse to be delivered to a time delay module to make a scattered signal measurement, measuring an asynchronous time value between the KSTAR timing board and the laser system injection signal. All functions are controlled by the embedded processor running on operating system within a single FPGA. It provides Ethernet communication interface and is configured with standard middleware to integrate with KSTAR. This controller has operated for two experimental campaigns including commissioning and performed the reconfiguration of logic designs to accommodate varying experimental situation without hardware rebuilding.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A single FPGA-based portable ultrasound imaging system for point-of-care applications

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

Hardware Implementation of Nakagami and Weibull Variate Generators

An efficient implementation of Nakagami- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> and Weibull variate generators on a single field-programmable gate array (FPGA) is presented. The hardware model first generates a correlated Rayleigh fading variate sequence and then transforms it into a sequence of Nakagami- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> or Weibull fading variates. A biquad processor facilitates the compact implementation of a Rayleigh variate generator with arbitrary autocorrelation properties. A combination of logarithmic and linear domain segmentations along with piece-wise linear approximations is used to accurately implement the nonlinear numerical functions required to transform the correlated Rayleigh fading process into Nakagami-m or Weibull fading processes. When implemented on a Xilinx Virtex-5 5VSX240TFF1738-2 FPGA, the fading simulator uses only 1.6% of the configurable slices, 1.2% of the DSP48E modules and 3 block memories, while operating at 120 MHz, generating 120 million complex variates per second. The throughput can be increased up to 373 MHz with this FPGA if two separate clock sources are utilized.

Ultrasonic scanner for in vivo measurement of cancellous bone properties from backscattered data

A dedicated ultrasonic scanner for acquiring RF echoes backscattered from the trabecular bone was developed. The design of device is based on the goal of minimizing of custom electronics and computations executed solely on the main computer processor and the graphics card. The electronic encoder-digitizer module executing all of the transmission and reception functions is based on a single low-cost field programmable gate array (FPGA). The scanner is equipped with a mechanical sector-scan probe with a concave transducer with 50 mm focal length, center frequency of 1.5 MHz and 60% bandwidth at -6 dB. The example of femoral neck bone examination shows that the scanner can provide ultrasonic data from deeply located bones with the ultrasound penetrating the trabecular bone up to a depth of 20 mm. It is also shown that the RF echo data acquired with the scanner allow for the estimation of attenuation coefficient and frequency dependence of backscattering coefficient of trabecular bone. The values of the calculated parameters are in the range of corresponding in vitro data from the literature but their variation is relatively high.

Design of SoC Verification System Based on Multi-FPGA

As one of the most advanced research field, the problem of SoC (System on a Chip) design is getting more and more attention. With the promotion of its theory and technique, SoC verification turns to one of the most significant part in the procedure of realizing a usable integrated circuit. And verification using FPGA (Field Programmable Gate Array) which must obey a set of strict technological process is a kind of general way. With the growing complexity and integrated scale of SoC design, a single FPGA chip could hardly satisfy the verification requirement. Then the method of verification using multi-FPGA is taken and expresses some advantages in some respects. Multi-FPGA verification is still in the initial step situation and has a broad developing space. The architecture of multi-FPGA verification platform is given in this paper, as well as some related key technical problem and solutions.