Single Field Programmable Gate Array Research Articles

Compact FPGA-based beamformer using oversampled 1-bit A/D converters

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

A high-speed optical mark reader hardware implementation at low cost using programmable logic

In today's fast-paced information-driven society, the need for accurate, timely, and cost-effective data collection is very critical. Optical mark reader (OMR) systems can be used to achieve these aspects. This paper describes the development of a low-cost and high-speed OMR system prototype for marking multiple-choice questions. The novelty of this approach is the implementation of the complete system into a single low-cost Field Programmable Gate Array (FPGA) to achieve the high processing speed. Effective mark detection and verification algorithms have been developed and implemented to achieve real-time performance at low computational cost. The OMR is capable of processing a high-resolution CCD linear sensor with 3456 pixels at 5000 frame/s at the effective maximum clock rate of the sensor of 20 MHz (4×5 MHz). The performance of the prototype system is tested for different marker colours and marking methods. At the end of the paper the proposed OMR system is compared with commercially available systems and the pro and cons are discussed.

Cascading delay line time-to-digital converter with 75 ps resolution and a reduced number of delay cells

A time-to-digital converter (TDC) is described, integrated on a single field-programmable gate array device with 75 ps single-shot resolution (LSB). Multiple-shot measurement statistically improves resolution to about 5 ps. The circuit is based on a counter and a two-step cascading delay line method that uses only 24 delay cells to provide 128 LSBs in the interpolator that resolves the time interval within the reference clock cycle. The relevant calibration method is also presented to obtain the time parameters of the TDC at the current temperature and voltage. This TDC can measure time intervals from 0 to 1.3 ms and the maximum range is only limited by the range of the counter. The temperature dependence is 0.1 ps/°C.

Field Programmable Gate Arrays Based Overcurrent Relays

This paper presents a novel technique of implementing overcurrent relays on field programmable gate arrays (FPGA), which can be used for the protection of distribution lines, large industrial motors and many equipments of the power system. Due to its reconfigurability, it gives an idea to implement many types of relays on the single FPGA board. In case of microprocessor based relays, many peripheral devices are required making the operation slower; but in the case of FPGA, the same can be realized with less number of peripherals, thus making the operation faster. The proposed overcurrent relay gives satisfactory results when simulated on the Xilinx FPGA, thus providing the best solution in the existing technologies.

High-resolution time-interval measuring system implemented in single FPGA device

The construction and design process of the time-interval measuring system of resolution 500 ps is discussed in this paper. Such a system can be applied in the construction of a real-time multichannel scalar (RTMS) designed for time-of-flight (TOF) mass spectrometry or lifetime decay measurements. Moreover, a high-resolution time-interval measuring system can be designed for light detection and ranging (LIDAR) system and ultrasonic flowmeters. We present the new high-resolution time-interval measuring system implemented in the single field programmable gate array (FPGA) structure.

FPGA based on-line tool breakage detection system for CNC milling machines

On-line tool breakage detection is one of the most important mechatronics problems in automated CNC machines. In this paper an on-line tool breakage detector for milling machines is described. The detector employs the cutting forces on the movement axis to compute the discrete wavelet transform of the resultant force. The novelty of this work is to apply the discrete wavelet transform of the resultant cutting force an autocorrelation algorithm to detect tool breakage in the form of an asymmetry weighting function and to implement the algorithm by using hardware signal processing techniques. The cutting force signals are taken from the current at the axis motor drivers for a sensorless instrumentation approach. The system has three parts: the signal conditioners, the data acquisition system and the hardware signal processing unit. The hardware signal processing unit was designed by following the system on-a-chip approach and it includes three application specific digital signal processing units, general synchronization, interface and control, implemented in a single field programmable gate array and a coefficient read-only memory. On-line detection and low-cost are guaranteed by following this approach. The detector system is a stand-alone unit and does not require microprocessors or computers to perform its task. Experimental results that show the overall system performance are presented.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

Abstract We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and “traditional” GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydrodynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

An implementation of fuzzy logic controller on the reconfigurable FPGA system

This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. Each implemented module forms a downloadable hardware object that is ready to configure the FPGA chip. Then, the FPGA chip is consequently reconfigured with one module at a time by using the run-time reconfiguration method. This implementation method is effective when a single FPGA chip cannot fit the FLC due to the limited size of its constituent cells. We test the proposed implementation method by building the FLC for the truck backer-upper control on VCC Corporation's EVC-1 reconfigurable FPGA board directly.

Delay-locked loop technique for temperature stabilisation of internal delays of CMOS FPGA devices

A delay-locked loop (DLL) technique for use with typical CMOS field programmable gate array (FPGA) devices is presented. It allows for temperature stabilisation of the internal delays of the devices, especially when the digital delay lines are designed. The voltage Vcc supplying the FPGA device is varied within a limited range by the DLL to stabilise the internal delays of the device under changes in the ambient temperature. The method is illustrated by presenting results of the realisation of an interpolating time counter with 200 ps resolution, implemented on a single CMOS FPGA device.

Real-time video surveillance system using a field programmable gate array

In this article, a stand-alone real-time video surveillance system is presented. This system monitors a scene through a fixed master camera with a wide field of view and then directs a slave camera to capture automatically high-resolution images of moving targets within the scene. Motion detection is achieved by means of background differencing using adaptive thresholding and a temporal filter to continually update the background. The user can set the system to respond to different types of targets on the basis of their size and shape. The system utilizes a single-field programmable gate array to control the capture and storage of image frames from the master camera, to perform all the necessary video-rate arithmetic and logical operations on images, and to generate all the signals needed to direct the slave camera. Results illustrating the highly successful operation of the system and comparisons with other reported surveillance systems are included. © 2000 John Wiley & Sons, Inc. Int J Imaging Syst Technol 11, 130–137, 2000

EmGen-a module generator for logic emulation applications

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multiphase design tasks, which is a very time-consuming process. Hence, shortening the time to emulation is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in hardware descriptive languages. Furthermore, the module generator can effectively generate a multiple field-programmable gate array (FPGA) macro for large macros that cannot fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their register transfer-level description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

Multi-function protective relay on FPGA

Protective relays play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. The design and implementation of a multi-function digital protective relay on a single field programmable gate array (FPGA) is discussed in this paper. The multi-function relay monitors the frequency and the voltage of the system. An output trip signal is set whenever the voltage value or the frequency value is outside pre-determined ranges. In addition, the multi-function relay estimates the rate of the frequency change. The FPGA (Xilinx 3030PC84-100) was used in the implementation.

FPGA realization of space-vector PWM control IC for three-phase PWM inverters

This paper presents a new circuit realization of the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using state of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. The output fundamental frequency can be adjusted from 0.094 to 1500 Hz. The pulse-width modulation (PWM) switching frequency can be set from 381 Hz to 48.84 kHz. The delay time for the PWM gating signals is adjustable. This SVPWM IC can also be included in the digital current control loop for stator current regulation. The designed SVPWM IC can be incorporated with a digital signal processor (DSP) to provide a simple and effective solution for high-performance AC drives. Simulation and experimental results are given to verify the implemented SVPWM control IC.

Nonlinearity correction of the integrated time-to-digital converter with direct coding

A method is presented for automated identification and correction of the nonlinearity error of the time-to-digital converter (TDC) with delay-line coding and 200 ps resolution, integrated on a single Field Programmable Gate Array (FPGA) device. The nonlinearity error is estimated using a statistical method based on a sufficiently large number N of measurements of random input time intervals having a uniform distribution within the input range of TDC. Then, the resulting estimate of the error function is used for training a two-layer neural network (NN) designed for correction of the nonlinearity error. Training of the NN is based on the fast Levenberg-Marquardt (LM) learning rule and the goal is to minimize the maximum nonlinearity error of the TDC. Experimental tests have shown, that using a relatively small number of N=5/spl times/10/sup 4/ identification measurements the maximum nonlinearity error of a TDC may be reduced from 1.37 LSB (least significant bit) to about 0.12 LSB (24 ps).

Single-chip interpolating time counter with 200-ps resolution and 43-s range

In this paper, we present a design and test results of the interpolating time counter implemented on a single field programmable gate array (FPGA) chip. The counter contains two 6-bit time-to-digital converters (TDCs), each having 200-ps resolution (LSB) within 10 ns range, and the 32-bit, 100-MHz real-time counter, which is also used for frequency measurement. The utilization of the logic cells on the FPGA chip is 93%. The software correction of the TDC's nonlinearity errors resulted in lowering the random error of the counter to 0.65 LSB or 129 ps (RMS).

Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters

Adaptive sample rate filtering has been shown to be an efficient and effective method of removing narrowband interference from broadband communication signals. The expression for the gradient for adaptive sample rate filtering is expressed in terms of the traditional adaptive filter gradient. Adaptive algorithms frequently use divide and square operations. Rather than implementing a generic multiplier in the adaptive section for the adaptive sample rate notch filter, we have developed a technique of optimizing an implementation of the squarer. In the sequential reciprocal circuit presented, we show how a numerator (scaling) can be easily incorporated into its design to achieve a general purpose divider. A Synopsis-synthesized VHDL description of a parallel reciprocal circuit is included for comparison. Both realizations have been demonstrated in an adaptive sample rate notch filter which has been downloaded into a single Xilinx XC4010 reconfigurable Field Programmable Gate Array (FPGA).

Computer-aided design of fuzzy systems based on generic VHDL specifications

In this paper, three types of fuzzy systems and related hardware architectures are discussed: standard fuzzy controllers, FuNe I fuzzy systems, and fuzzy classifiers based on a neural network structure. Two computer-aided design (CAD) packages for automatic hardware synthesis of standard fuzzy controllers are presented: a hard-wired implementation of a complete fuzzy system on a single or multiple field programmable gate arrays (FPGA) and a modular toolbox called fuzzyCAD for synthesis of reprogrammable fuzzy controllers with architectures due to specified designer constraints. In the fuzzyCAD system, an efficient design methodology has been implemented which covers a large design space in terms of signal representations and component architectures as well as system architectures. Very high speed integrated-circuits hardware-description language (VHDL) descriptions and usage of powerful synthesis tools allow different technologies to be targeted easily and efficiently. Properties and hardware realizations of fuzzy classifiers based on a neural network are introduced. Finally, future perspectives and possible enhancements of the existing toolkits are outlined.

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications.

Design and implementation of a hardware fuzzy inference system

This paper discusses the design of a dedicated hardware fuzzy inference system based on the generalized modus ponens (GMP) inference rule, the “mini” fuzzy implication function, the “max-min” fuzzy composition rule, and the center of gravity (COG) defuzzification method. As a special case, the implementation of a two-input (antecedents), one-output (consequent) fuzzy inference system based on the general design idea was implemented on a single field programmable gate array (FPGA) chip with an extra EPROM for defuzzification. Circuitry details and performance data are included. Additional issues such as extendibility and adaptability are also discussed.

Efficient FIR filter architectures suitable for FPGA implementation

This paper describes efficient architectures for FIR filters. By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>