Single Event Transient Pulse Width Research Articles

Novel layout technique for single-event transient mitigation by the groove structure

Based on the damage mechanism of single-event transient (SET) in a MOS device, a new irradiated reinforcement uniaxial strained Si Nano NMOSFET device is further proposed, and the new structure device has no effect on the electrical properties of its original structure. Moreover, the new reinforced device of groove structure can efficiently reduce not only charge collection but also SET pulse widths (WSET). Compared with the conventional NMOS and drain-wall structure, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in the effective area. Therefore, the successful development of the research results will play a positive role in promoting the theoretical and technological progress of high-performance radiation-resistant core electronic components and lay a foundation and create conditions for their application in space radiation and nuclear radiation.

Characterization and modeling of Single Event Transient propagation through standard combinational cells

Analysis of Single Event Transient (SET) effects is an important step in the design of radiation-hardened integrated circuits for space missions. Because the simulation of SET effects in a complex design would be very time-consuming, appropriate SET models are required to simplify and speed up the SET analysis. In this paper, we demonstrate an approach for deriving an analytical SET propagation model from the simulation-based characterization of standard cells. We have performed detailed characterization of standard combinational cells designed in IHP's 130 nm CMOS technology, using Cadence Spectre simulations. The simulation results have shown that significant SET broadening may occur across short combinational paths composed of up to ten logic gates, and supply voltage and temperature variations may enhance the SET broadening. By fitting the simulation results, an analytical model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model expresses the propagated SET pulse width in terms of gate's size factor, load capacitance, supply voltage and temperature. Using the proposed model allows for estimating the SET pulse width across any combinational path composed of characterized standard cells. The model was verified on selected combinational paths, and the average relative error with respect to simulations was 6.4 %.

Efficacy of Spatial and Temporal RHBD Techniques at Advanced Bulk FinFET Technology Nodes

Single-event (SE) performance of a variety of radiation-hardened by design (RHBD) flip flop (FF) circuits are evaluated at the 7-nm and 5-nm bulk FinFET nodes. For a given RHBD technique, the 5-nm node design has a single-event upset (SEU) cross-section an order of magnitude higher than that at the 7-nm node. Such an increase in SEU cross-section was not seen with scaling of previous nodes. Simulations indicate that the increase in SEU cross-section is due to disproportionate changes in single-event transient pulse-widths and sensitive areas after an ion strike. A figure-of-merit is proposed to quantify the efficacy of a given RHBD technique. RHBD FF designs are evaluated using this metric to show the efficacy of spatial and temporal RHBD techniques at the 7-nm and 5-nm technology nodes at both nominal and reduced supply voltage operations.

Comparative Analysis of Single Event Transients in InGaAs-OI/Bulk/BOI FinFETs for SET-Tolerant InGaAs/Ge-OI Complementary FinFET Circuits

The III-V/Ge complementary-FinFET (C-FinFET) based integrated circuits are more susceptible to radiation-induced single event transients (SET) than silicon counterparts. In this paper, the single event transients in n-channel InGaAs structures such as stacked 5-fin InGaAs-Bulk, InGaAs-Body on Insulator (InGaAs-BOI) and InGaAs-on-Insulator (InGaAs-OI) FinFETs are analyzed and optimized for SET-tolerant InGaAs/Ge-OI C-FinFET circuits. The SET analysis is done for these structures for different Linear Energy Transfer (LET), vertical strike positions, normal/angular strike incidences, gate underlap/overlap and oxide materials. The SET pulse widths for InGaAs/Ge-OI C-FinFETs are determined for different load capacitances, LETs, supply voltages and PMOS ON current. It is observed that the SET pulsewidth is lesser for InGaAs-OI/Ge-OI C-FinFETs compared to other two chosen structures. However, having the advantages of both InGaAs-Bulk and InGaAs-OI structures, the InGaAs-BOI FinFET with lesser pulsewidth than InGaAs-Bulk FinFET is a better candidate to use in radiation-prone environment.

A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits

As technology continuously shrinks, radiation-induced soft errors have become a great threat to the circuit reliability. Among all the causes, Single-Event-Transient (SET) is the dominating one for the radiation-induced soft errors. SET-induced soft errors can be mitigated by multiple methods. In terms of area and power overhead, blocking SET propagation is considered to be the most efficient way for soft error reduction. It is found that the SET pulse width can be shrunk by pulse quenching effect, which can be utilized to mitigate soft errors without introducing any area and power overhead. In this paper, we present an effective detailed placer to exploit pulse quenching effect for soft error reduction in combinational circuits. In our method, the quenching effect enhancement is globally optimized while the cell displacement is minimized. The experimental results demonstrate that our method reduces the soft error vulnerability of the circuits by \(29.53\% \) vs. \(18.38\% \) of the state-of-the-art solution. Meanwhile, our method has a minimal effect on the displacement and half-perimeter wire-length (HPWL) compared to the previous solutions, which means a minimum timing influence to the original design.

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Single-event transient (SET)-induced soft errors are becoming a more significant threat to the reliability of electronic systems in space, especially for advanced technologies. The SET pulse width, which is vulnerable to SET propagation, is a critical parameter for developing SET mitigation techniques. This paper investigates the pulse-broadening effect in the process of SET propagation in logic circuits and the SET-sensitive region distribution in the layout using the pulsed-laser mapping technique in logic circuits implemented with 28 nm Ultra-Thin Body and BOX (UTBB) FDSOI technology. The experiments were carried out at the Naval Research Laboratory (NRL) to measure the SET-induced errors and map the SET-sensitive region distribution at various clock frequencies and laser energy levels. The results illustrate that the number of errors increases with the clock frequency and energy for combinational logic circuits and that the flip-flop SEU rate is less sensitive to clock frequency. The SET pulse-broadening effect was also observed using SET mapping for an OR gate chain at different laser energy levels. In addition, the simulation results revealed the mechanism of the SET pulse-broadening effect in an OR gate chain.

PS-BBICS: Pulse stretching bulk built-in current sensor for on-chip measurement of single event transients

The bulk built-in current sensor (BBICS) is a cost-effective solution for detection of energetic particle strikes in integrated circuits. With an appropriate number of BBICSs distributed across the chip, the soft error locations can be identified, and the dynamic fault-tolerant mechanisms can be activated locally to correct the soft errors in the affected logic. In this work, we introduce a pulse stretching BBICS (PS-BBICS) constructed by connecting a standard BBICS and a custom-designed pulse stretching cell. The aim of PS-BBICS is to enable the on-chip measurement of the single event transient (SET) pulse width, allowing to detect the linear energy transfer (LET) of incident particles, and thus assess more accurately the radiation conditions. Based on Spectre simulations, we have shown that for the LET from 1 to 100 MeV cm2 mg−1, the SET pulse width detected by PS-BBICS varies by 620–800 ps. The threshold LET of PS-BBICS increases linearly with the number of monitored inverters, and it is around 1.7 MeV cm2 mg−1 for ten monitored inverters. On the other hand, the SET pulse width is independent of the number of monitored inverters for LET > 4 MeV cm2 mg−1. It was shown that supply voltage, temperature and process variations have strong impact on the response of PS-BBICS.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Characterization of single-event transients induced by high LET heavy ions in 16 nm bulk FinFET inverter chains

Single-event transient (SET) distributions and cross-sections are characterized for 16 nm bulk FinFET inverters with different threshold voltages and driving strengths using the heavy ion 181Ta with the energy of 1.07GeV and the Linear Energy Transfer (LET) of 85 MeV·cm2/mg. Lower threshold voltage makes shorter SET pulses and smaller cross-section, and reduces the upper limit of the SET pulse width, which is advantageous to harden the FinFET gates against the high LET heavy ion irradiation. Enhancing the driving strength changes the layout topology, leading to complicated impact on the radiation sensitivity for FinFET inverters. The source region is laid at one side of the drain region in P or N type transistor of the inverter with driving strength X1 (INV1), while there are two source regions at both sides of the drain region in P or N type transistor in the inverter with driving strength X2 (INV2), which makes INV2 is more SET tolerant than INV1. There are interdigitated two drain regions and three source regions in P or N type transistor of the inverter with driving strength X4 (INV4), which expands the sensitive area and cross-section. The test results indicate that the max SET pulse width is approximately proportional to the ratio of sensitive area to driving strength for the FinFET inverters, that is the max SET pulse width of INV4 is between INV1 and INV2.

Research on temperature sensitivity of Single-event Transient pulse width in 28-nm bulk technology

The influence of temperature on single-event transient (SET) pulse width has always been a hot issue in the field of anti-irradiation. Based on 3D-TCAD simulation, the temperature sensitivity of the SET pulse width of 28-nm bulk devices has been studied. The simulation results show that the electrical characteristics of the device shows an anti-temperature effect, but the worst case of SET pulse width still occurs at high temperature rather than low temperature. The influence of the triple-well structure on the temperature sensitivity of the SET pulse width has also been studied. The N+ deep well can significantly increase the SET pulse width when hitting NMOS device and enhance the temperature sensitivity of the SET pulse width. The research content of this article will provide reference for the design of radiation resistant chip.

Neutron-Induced Pulsewidth Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain-Based Test Structure

This work presents measured data showcasing neutron-radiation induced Single Event Transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulse width distributions. The SET pulse width distributions are obtained from a high density, array-based characterization-vehicle, implemented in 65nm planar CMOS and 16nm FinFET processes, featuring a tunable, high resolution pulse-shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro employs standard logic gate-chains in varying lengths, threshold voltages (VTH) and transistor width flavors as the Devices-Under-Test (DUTs). Measured irradiation data for a range of operating voltages from nominal down to near-threshold reveals the relative impact of the chosen design parameters such as VDD, VTH, device width and the logic chain length as well as their interplay, impacting the overall soft-error susceptibility and the sampled pulse width distributions among the different standard gate types.

SET characterization of 130 nm flash-based FPGA device

Low-power, flash-based field programmable gate arrays (FPGAs) have attracted significant attention in space electronic systems due to their re-programmability feature and non-volatility. In this study, we discussed a method for continuous and synchronous measurement of single event transient (SET) pulse widths in the ProASIC3 flash-based FPGA. The dedicated SET test system and irradiation set-up were implemented under heavy-ion irradiation. The SET generation cross-sections, pulse widths and capture characteristics in combinational logic chains were analyzed. The results indicated that the SET pulse width distribution exhibited a log-normal function and the SET capture probability linearly increased with the working frequency.

Mitigation Technique for Single Event Transient via Pulse Quenching

With the technology scaling down, the single event transients produced in the combinational circuit lead to an increasing threat to reliability. In this paper, Dummy Gate Enhanced Charge Sharing (DGECS) technique is proposed to mitigate single event transients, and enhances the pulse quenching of logic cells by increasing the charge sharing between key transistors. Mixed-mode 3-D technology computer aided design simulations were carried out with commercial 65nm dual-well CMOS technology. The simulation results show that the proposed layout technique can significantly reduce single event transient pulse widths and even completely quench transient pulses.

Monitoring of Particle Count Rate and LET Variations With Pulse Stretching Inverters

This study investigates the use of pulse stretching (skew-sized) inverters for monitoring the variation of count rate and linear energy transfer (LET) of energetic particles. The basic particle detector is a cascade of two pulse stretching inverters, and the required sensing area is obtained by connecting up to 12 two-inverter cells in parallel and employing the required number of parallel arrays. The incident particles are detected as single-event transients (SETs), whereby the SET count rate denotes the particle count rate, while the SET pulsewidth distribution depicts the LET variations. The advantage of the proposed solution is the possibility to sense the LET variations using fully digital processing logic. SPICE simulations conducted on IHP's 130-nm CMOS technology have shown that the SET pulsewidth varies by approximately 550 ps over the LET range from 1 to 100 MeV ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ·mg <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The proposed detector is intended for triggering the fault-tolerant mechanisms within a self-adaptive multiprocessing system employed in space. It can be implemented as a standalone detector or integrated in the same chip with the target system.

Effect of Cell Placement on Single-Event Transient Pulse in a Bulk FinFET Technology

In this article, five different cell placement structures of a vertical inverter chain were designed in a commercial bulk FinFET technology to investigate the effect of cell placement on a single-event transient (SET) pulse. 3-D TCAD mixed-mode simulation indicated that the cell placement has a significant effect on SET pulsewidths. Heavy-ion experiments at Cyclotron in the China Institute of Modern Physics in Lanzhou also indicated that the effect of cell placement on the SET pulse is obvious. The experiment also indicated that the effect of cell placement on P-hit SET is larger than that on N-hit SET, and charge sharing in vertical was becoming as important as that in horizontal.

Relationship between ion track characteristics and single event transients in nanometer inverter chain

Ions with the same linear energy transfer (LET) value, but different energies and species have various ion track characteristics, and thus induce different single event transient (SET) responses in combinational logics. As the technology feature size shrinks, this issue continues to be serious. The research of the relationship between ion track characteristics and SETs in the nanometer combinational logic circuits is of great significance for accurately predicting the soft error rates of nanometer devices used in spacecraft. The combinational logic circuit investigated in this paper is a 65 nm bulk silicon complementary metal oxide semiconductor (CMOS) technology inverter chain. The three-dimensional TCAD model of the inverter chain is established, and the particle transport program for the ion track in bulk silicon is developed by Geant4. The track characteristics of high- and low-energy ions (the energy of low-energy ions is less than 10 MeV·n&lt;sup&gt;–1&lt;/sup&gt;, the energy of high-energy ions ranges from tens of MeV·n&lt;sup&gt;–1&lt;/sup&gt; to hundreds of MeV·n&lt;sup&gt;–1&lt;/sup&gt;) which have the same LET value are compared with each other. Based on the coupled simulation of TCAD and Geant4, the difference in SET pulse widths, induced by ions with the same LET value but different energies, are investigated. It is found that when the energy per nucleon ratio of high-energy ion to low-energy ion increases, the difference in electron-hole pair densities near the center axis of the ion track is more significant, and thus the difference in SET pulse widths is larger. If the energy per nucleon ratio is similar, raising the LET value of ions can increase the difference in electron-hole pair densities on the same radial scale of the ion tracks, and make the SET pulse width difference more obvious. For the high- and low-energy ions with the same LET value, the single event charge generations are different. On the other hand, the change of the ion incident angle results in different charge collections. The coupling of these two factors makes the difference in SET pulse widths dependent on the incident angle of ions. In addition, the influence of ion track characteristics on SET has a weak correlation with the bias voltage of the inverter chain.

A Physics-Based Single Event Transient Pulse Width Model for CMOS VLSI Circuits

The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 $nm$ CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that considers the device electrostatics is necessary to predict and mitigate these soft errors in VLSI circuits. In this article, a physics-based bias-dependent model is developed to determine the SET pulse width of a double-gate (DG) CMOS inverter with the heavy-ion strike on OFF state NMOS. The output voltage perturbations due to ion strike in the CMOS inverter and the SET pulse width model are derived from the bias-dependent SET current model previously reported. The variations in the output voltage of the inverter and the pulse width obtained from the developed model for different Linear Energy Transfer (LET), supply bias, strike positions, device dimensions, and load capacitances are validated with TCAD mixed-mode simulations.

Sensitivity of SET Pulse-Width and Propagation to Radiation Track Parameters in CMOS Inverter Chain

Single-event transient (SET) due to heavy-ion strike is a serious reliability concern for devices operated in radiation environment. Due to technology scaling, nodal capacitance decreases which increases the SET vulnerability. In this paper, the sensitivity of SET pulse width in 45 nm bulk and SOI MOSFET to linear energy transfer (LET), heavy-ion track length, angle of strike, characteristic radius, and characteristic time of the track is analysed. The modification of SET pulse width while propagating through 45 nm bulk-and SOI-based CMOS chain of inverters and its dependence on aforementioned radiation parameters is also analysed. The results show that all the pulses produced in SOI-based inverter chain get attenuated during propagation and do not reach the last stage. However, in the case of bulk, any SET having pulse width greater than 37 ps (measured using full width at half maximum) propagates and reaches the last stage of the inverter chain. Thus, the SOI devices are more immune to SET compared to the bulk, for different heavy-ion track parameters.

An Approach to Emulate and Validate the Effects of Single Event Upsets using the PREDICT FUTRE Hardware Integrated Framework

Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.

Supply Voltage and Temperature Dependence of Single-Event Transient in 28-nm FDSOI MOSFETs

Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.