Single Event Functional Interrupt Research Articles

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

Single Event Functional Interrupt (SEFI) poses a severe threat to the normal operation of spacecraft. This paper investigates SEFI in Analog-to-Digital Converters (ADCs) with storage units using precision positioning of pulsed lasers. Based on the experiment, it was discovered that a bit flip in the configuration registers in ADCs results in changes in parameters such as digital filter frequency, operating mode, and gain, leading to an upward or downward offset of ADC output codes. Similarly, a bit flip in the calibration registers also causes ADC output codes to shift upwards or downwards, or even output a value of zero. Furthermore, it was observed that SEFI phenomena can occur due to current latch-up in ADC input pins, causing the inability to read or write data in ADC storage units. This current latch-up can be resolved through power cycling or configuring the pins into a high-impedance state. This work highlights the significance of SEFI phenomena in ADCs, emphasizing the serious threat posed by storage unit flipping-induced SEFI to the proper functioning of ADCs. Moreover, the SEFI phenomenon caused by current latch-up in input pins is difficult to detect in practice, making it highly elusive. Once it occurs, it severely impacts the functionality of ADCs.

Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA

Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant.

Observation framework of errors in microprocessors with machine learning location inference of radiation-induced faults

This paper presents a non-intrusive failure reason capturing approach for processor-based system-on-a-chip (SoC) integrated as an intellectual property (IP). It provides diagnostic information about the origin of single-event upsets (SEU) in the context of technology qualification to radiations. Thanks to the combination of trace events buffering and error detection with triggering mechanisms, the module is able to capture an execution trace containing the error propagation, using only 1 KB of memory. The execution trace is supplemented by a configurable set of pipeline registers. For single-event functional interrupt (SEFI), we also propose a technique based on a machine-learning algorithm to find from which register the SEU comes from. The captured CPU trace is processed by a classification algorithm, trained on a fault-injection campaign database and providing an accuracy score up to 87 %.

Radiation testing of a commercial 6-axis MEMS inertial navigation unit at ENEA Frascati proton linear accelerator

We present the first results of a novel collaboration activity between ENEA Frascati Particle Accelerator Laboratory and University La Sapienza Guidance and Navigation Laboratory in the field of Radiation Hardness Assurance (RHA) for space applications.The aim of this research is twofold: (a) demonstrating the possibility to use the TOP-IMPLART proton accelerator for radiation hardness assurance testing, developing ad hoc dosimetric and operational procedures for RHA irradiations; (b) investigating system level radiation testing strategies for Commercial Off The Shelf (COTS) components of interest for SmallSats space missions, with focus on devices and sensors of interest for guidance, navigation and control, through simultaneous exploration of Total Ionizing Dose (TID), Displacement Damage (DD) dose and Single-Event Effects (SEE) with proton beams.A commercial 6-axis integrated Micro Electro-Mechanical Systems (MEMS) inertial navigation system (accelerometer, gyroscope) was selected as first Device Under Test (DUT). The results of experimental tests aimed to define an operational procedure and the characterization of radiation effects on the component are reported, highlighting the consequence of the device performance degradation in terms of the overall navigation system accuracy. Doses up to 50 krad(Si) were probed and cross sections for Single-Event Functional Interrupt (SEFI) evaluated at a proton energy of 30 MeV.

A Methodology to Analyze the Fault Tolerance of Demosaicking Methods against Memory Single Event Functional Interrupts (SEFIs)

Electronic circuits in harsh environments, such as space, are affected by soft errors produced by radiation. A single event functional interrupt (SEFI) can affect the behavior of a memory chip, with one or more rows, columns or even the whole device producing a wrong value when reading a set of stored bits. This problem may affect raw Bayer images stored in satellites and other spacecraft. In this paper, we present a methodology to analyze how different interpolation algorithms behave when they try to reconstruct the affected Bayer images into standard red, green and blue (RGB) images. This methodology can be used to compare and develop new fault-tolerant algorithms. The proposed methodology has been illustrated by studying a subset of interpolation algorithms. The results obtained from this example show that the interpolation algorithms that traditionally offer better results in a normal operation (in the absence of errors) are not always the best when SEFI errors are present in the Bayer images.

Single Event Effect Characterization of High Speed Serial JESD204B Data Receiver

This work proposed and discussed a serial JESD204B data receiver and conducted a single event effect test on it. The test is used to analyzed the Single Event Upset (SEU), single Event Latch-up (SEL) and Single Event Functional Interrupt (SEFI). The purpose of the test is to determine if single event effect caused the chip to crash or increase the on-track error rate. The results show that the circuit has a strong ability to resist Single event effect.

SEFI Modeling in Readout Integrated Circuit Induced by Heavy Ions at Cryogenic Temperatures

This paper presents a modeling approach of single-event functional interrupt (SEFI) which takes into account all the physical and electrical processes from the radiation particle down to the event at the system level. This paper is focused on the evaluation of SEFI sensitivity by experimental and simulation analyses of a readout integrated circuit (ROIC) designed by Sofradir for their infrared image sensors. Relevant correlations between simulation and experimental results of SEFI cross sections for heavy ions are presented and discussed. The simulation results confirm the strong SEFI robustness of the ROIC at 57 K.

Dose and Single-Event Effects on a Color CMOS Camera for Space Exploration

This paper focuses on the radiation-induced dose and single-event effects (SEEs) on a color CMOS camera designed for space missions. The γ -ray and proton tests are used to evaluate the tolerance against cumulative dose effects. The dark current of the image sensor is the main parameter impacted by dose effects. Heavy ions testing is performed to evaluate SEEs. single-event upset, single-event functional interrupt, and single-event latchup have been observed and mitigation techniques were proposed for specific space missions.

Heavy ion-induced single event effects in active pixel sensor array

The complementary metal-oxide-semiconductor (CMOS) active pixel sensors (APSs) can easily be susceptible to heavy-ion radiation in space applications. In this paper, the single event effects (SEEs) of pinned photodiode (PPD) active pixel sensor array exposed to heavy ion (Tantalum, Xenon, Krypton) with linear energy transfer (LET) (37, 50.34 and 81.35 MeV·cm2/mg) have been studied. During the heavy ion exposure, all devices were fully functional and integration time was changed, no single event latch-up (SEL) and single event functional interrupt (SEFI) happened. However, dark background with pixel clusters in a frame, which indicates the single event transient (SET) effect were observed. The number of the pixel clusters, total collected charge and cluster size were analyzed in detail. Finally, SRIM simulations were conducted on a PPD in order to predict the number of the electron-hole pairs generated by a heavy ion.

Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment

Electromagnetic radiation effects can cause several types of errors on traditional SRAM-based registers such as single event upset (SEU) and single event functional interrupt (SEFI). Especially in aerospace where radiation is quite intense, the stability and correctness of systems are greatly affected. By exploiting the beneficial features of high radiation resistance and non-volatility, spin-transfer torque RAM (STT-RAM), a kind of emerging nonvolatile memory (NVM), is promising to be used as registers to avoid errors caused by radiation. However, substituting SRAM with STT-RAM in registers will affect system performance because STT-RAM suffers from long write latency. The early write termination (EWT) method has been accepted as an effective technique to mitigate write problems by terminating redundant writes.Based on the above background, this paper proposes to build registers by STT-RAM for embedded systems in rad-hard environment. Targeting the microarchitecture level of pipeline, the impact of architecting STT-RAM-based registers is discussed considering data hazard due to data dependencies. Furthermore, integrated with the EWT technique, Read Merging and Write Skipping methods are proposed to eliminate redundant normal reads and writes. As a result of carrying out these actions, the energy and performance can be improved greatly. The results report 70% (and 77%) and 39% (and 47%) improvements on performance (and energy) by the proposed Read Merging and Write Skipping compared to the cases where STT-RAM is naively used as registers and intelligently used by integrating EWT, respectively.

Seu and Sefi error detection and correction on a ddr3 memory system

This paper presents an embedded design that performs a novel Single Event Upset (SEU) and Single Event Functional Interrupt (SEFI) detection and recovery technique for DDR3 Synchronous Dynamic Random-Memories (SDRAM) memories in space applications. Using a memory system composed of four devices, this SEFI recovery method allows to restore the content of one entire device using the data and the Error Correction Code (ECC) bits stored in the other three devices. This design is implemented on a Xilinx Zynq-7000 System on Chip (SoC). The SEU detection and the recovery functionality is implemented on a Xilinx Zynq as an AXI bus peripheral. This peripheral is connected with the Processing System (PS) of the device via AXI bus, where a SEFI detection algorithm is implemented in a software application that runs in the ARM Cortex-A9. The developed technique also allows to inject errors to test the whole functionality.

Impact of D-Flip-Flop Architectures and Designs on Single-Event Upset Induced by Heavy Ions

This paper highlights the impact of design on the single-event upset (SEU) sensitivity of D-flip-flops (DFFs) used in a readout circuit (ROIC) under heavy ions. New experimental data obtained at the University of Louvain for several designs are presented. The single-event effect (SEE) prediction tool multi-scale single event phenomena predictive platform is used to investigate the failure occurrences at the circuit level as a function of the design. In some cases, design specificities allow for increasing in the SEU robustness of the DFF. However, it appeared that cryogenic temperatures limit the impact of the design on the SEU sensitivity of DFFs. The results show a very limited impact of the temperature on the SEU occurrence, independent of the layout. These results are consistent with the experimental data presented in recent works regarding single-event transient and single-event functional interrupt. These results allow for performing irradiation tests of complementary metal–oxide–semiconductor IR detector (ROIC) at room temperature instead of cooling down the device during the SEE measurements.

Update of Single Event Effects Radiation Hardness Assurance of Readout Integrated Circuit of Infrared Image Sensors at Cryogenic Temperature.

This paper review presents Single Event Effects (SEE) irradiation tests under heavy ions of the test-chip of D-Flip-Flop (DFF) cells and complete readout integrated circuits (ROIC) as a function of temperature, down to 50 K. The analyses of the experimental data are completed using the SEE prediction tool MUSCA SEP3. The conclusions derived from the experimental measurements and related analyses allow to update the current SEE radiation hardness assurance (RHA) for readout integrated circuits of infrared image sensors used at cryogenic temperatures. The current RHA update is performed on SEE irradiation tests at room temperature, as opposed to the operational cryogenic temperature. These tests include SET (Single Event Transient), SEU (Single Event Upset) and SEFI (Single Event Functional Interrupt) irradiation tests. This update allows for reducing the cost of ROIC qualifications and the test setup complexity for each space mission.

Experimental study about single event functional interrupt of ferroelectric random access memory induced by 30-90 MeV proton

Ferroelectric random access memory (FRAM) is a promising memory for space application. The performance of FRAM under irradiation environment should be investigated, especially under proton irradiation environment, which dominates the particles in the space environment. The experiments on single event effects are carried out for two types of FRAMs (FM22L16 and FM28 V100) based on the proton cyclotron of China institute of atomic energy. Both dynamic and static mode are tested for each chip under the irradiation of proton in an energy range from 30 MeV to 90 MeV. Single event upsets (SEUs) and single event functional interrupts (SEFIs) are observed only on FM22L16, where the SEFI is recorded as a significantly transient error with or without memory cell upsets. The SEFI can be subdivided into soft SEFI and hard SEFI according to whether those significantly transient errors disappear or not when the irradiation is paused. Single event effect performances of FM22L16 are accurately described, and the SEFI cross section in an energy range from 50 MeV to 90 MeV is obtained experimentally. The cross section of SEFI increases with proton energy increasing and reaches 10<sup>-3</sup>/cm<sup>2</sup> at 90 MeV. To further study the mechanism of SEFI, the pulsed laser beam with a wavelength of 1064 nm is used to pinpoint the sensitive area of SEFI in the FRAM. Pulsed laser experiment is easy to carry out when single pulsed laser radiates on the device from the back side. Results show that a certain part in peripheral circuit is detected as a sensitive area to SEFI. The sensitive area could be a register or buffer which is vulnerable to irradiation. Only SEUs are observed when the pulsed laser radiates others area of peripheral circuit and memory cell. A hypothesis that a micro latch-up in the CMOS-based peripheral circuit leads to the SEFI is proposed to explain the test results, for the CMOS-based peripheral circuit is sensitive to irradiation. The further reason is the energy deposition in silicon substrate by protons with energies ranging from 30 MeV to 90 MeV through nuclear reaction, which triggers the silicon controlled rectifier structure in the FRAM peripheral circuit. According to the hypothesis, a transient current should be generated in the peripheral circuit when the micro latch-up happens. The transient current is observed on the output of device by using a high frequency oscilloscope which demonstrates the reasonability of the hypothesis.

Measurement of single event effects induced by alpha particles in the Xilinx Zynq-7010 System-on-Chip

ABSTRACTSingle event effect susceptibility of the Xilinx Zynq-7010 System-on-Chip (SoC) was investigated. Seven hardware blocks in the Zynq-7010 SoC were tested for single event effects using americium-241 alpha radiation source. Four error types, data error, single event upset and functional interrupt events, time-out, and system halt, were observed in different blocks under test. The dynamic cross sections of the different blocks were obtained and the reasons of some critical error types were analyzed.

Radiation Hard Contactless Angular Position Sensor Based on Hall Effect

The results of the total ionizing dose (TID) and single event effect (SEE) tests on the contactless angular position sensor based on Hall effect are presented. The TID testing reveals that the devices are resistant to the gamma radiation exhibiting only a slight increase in the supply current, not more than 1 % of the initial values. In general, both the serial peripheral interface (SPI) output errors and analog output errors have recovered to their initial values after annealing at high temperatures. Only the biased sample with magnet showed a significant increase of the analog output error at higher radiation levels and did not return to its initial value, it remained about a 56 % higher. Nevertheless, the error is still within the limits for space application of the sensor. SEE tests were performed up to linear energy transfer (LET) levels of 67.7 MeV $\cdot $ cm2/mg and the sensors experienced neither single event latch-up (SEL) nor single event transient (SET). The upper limit of cross section for single event functional interrupt (SEFI) was found by Weibull fit as being $3.53\cdot 10^{\mathrm {-6}}$ cm2 and the LET threshold was 15.1 MeV $\cdot $ cm2/mg. The SEFI rates were calculated by means of the CREME96 for geostationary orbit (GEO) and the orbit of the International Space Station (ISS). Calculations were performed for minimum solar and peak 5 minutes environment, and in the case of the ISS orbit also trapped particles and magnetic weather conditions were included.

Irradiation Damage Tests on Backside-Illuminated CMOS APS Prototypes for the Extreme Ultraviolet Imager On-Board Solar Orbiter

Complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) prototypes made using 0.18 μm technology process have been developed for the Extreme Ultraviolet Imager of the Solar Orbiter mission. Backside illuminated CMOS APS devices, i.e., 256 × 256 pixels area, 10 μm pixel pitch with different pixel designs have been fully characterized in the visible and in EUV wavelengths. A set of irradiation tests were carried out to investigate the degradation of the devices expected in the space environment conditions of Solar Orbiter. Total ionizing dose effects from grounded measurements are presented up to 150 krad[SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ]. The prototype sensors show the immunity to single-event latch up at linear energy transfer's of 67.7 MeV cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg but were observed to suffer from strong degradations after proton irradiation test (with a cumulated fluence up to 4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> protons/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and from single event functional interrupt.

Single-Event Effects in CMOS Image Sensors

In this paper, 3T active pixel sensors (APS) are exposed to heavy ions (N, Ar, Kr, Xe), and single-event effects (SEE) are studied. Devices were fully functional during exposure, no single-event latch-up (SEL) or single-event functional interrupt (SEFI) happened. However, single-event transient (SET) effects happened on frames: line disturbances, and half or full circular clusters of white pixels. The collection of charges in cluster was investigated with arrays of two pixel width (7 and 10 μm), with bulk and epitaxial substrates. This paper shows technological and design parameters involved in the transient events. It also shows that STARDUST simulation software can predict cluster obtained for bulk substrate devices. However, the discrepancies in epitaxial layer devices are large-which shows the need for an improved model.

Heavy-Ion Radiation Characteristics of DDR2 Synchronous Dynamic Random Access Memory Fabricated in 56 nm Technology

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 <TEX>$MeVcm^2/mg$</TEX>. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

Digital Control for Radiation-Hardened Switching Converters in Space

Single-event hardening solutions for two converter designs with digital control are considered for space radiation environments: 1) a boost converter using static random access memory (SRAM)-based field programmable gate arrays (FPGAs). In this case the hardening approach is based on duplication at both the logic and device levels and on a nondisruptive resynchronization mechanism that ensures the converter operation if single-event functional interrupt occurs. 2) An integrated buck converter that uses redundancy at the register level, as well as modification of the very high speed integrated circuit (VHSIC) hardware description language (VHDL) code. These hardening techniques are validated through experiments and simulations.