Single-ended Circuit Research Articles

High-Order Quasi-Elliptic-Type Single-Ended and Balanced Wideband Bandpass Filters Using Microstrip-to-Microstrip Vertical Transitions

High-order single-ended and balanced wideband bandpass filters (BPFs) with quasi-elliptic-type (QET) responses are reported. Firstly, a fifth-order wideband BPF based on a two-layer microstrip-to-microstrip vertical transition with two shunt open-circuit-ended two-section microstrip stubs at the input and output ports, respectively, is designed. Compared to a typical third-order vertical transition, two more transmission poles (TPs) along with a pair of close-to-passband transmission zeros (TZs) are attained. Next, an application to design a ninth-order QET balanced wideband BPF using a vertical transition is carried out. Owing to the used slotline resonator, an intrinsic common-mode (CM) suppression capability is obtained for it. The RF operational and design principles of these BPF devices are detailed by means of their relevant transmission-line-(TL)-based equivalent circuits. For experimental-validation purposes, two microstrip prototypes corresponding to a 3-GHz fifth-order wideband BPF and a 2-GHz ninth-order balanced wideband BPF are developed and tested. The measured single-ended and balanced BPF circuits feature sharp-rejection QET responses with two close-to-passband TZs and stopband-power-attenuation levels above 27.3 dB and 43.66 dB, respectively. The measured CM suppression levels for the balanced BPF device are higher than 34.59 dB from DC to 5 GHz.

Array Sensor Output Signal Detection System Signal Conditioning Circuit Design

The signal output by the array sensor is generally very weak, with a large dynamic range and a wide range of signal frequencies. In order to solve the problem of accurate measurement of weak signals with wide frequency and large dynamic range, this paper proposes a design method of sub-band filtering and variable gain amplifying circuit based on the analog switch, divides the signal into four frequency bands, and designs four groups of second-order voltage control filter, and adjust the magnification for different frequency signals, and only need to switch the corresponding resistance and capacitance to realize the switching of signal processing circuits of different frequency bands, which greatly optimizes the circuit structure. In order to reduce the interference in the transmission process, a single-ended differential circuit is designed to transmit the processed signal to the subsequent acquisition system for acquisition. After the simulation test, the signal conditioning circuit can effectively improve the signal-to-noise ratio of the detection signal and improve the measurement accuracy.

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

As deep learning techniques such as Convolutional Neural Networks (CNNs) are widely adopted, the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip (SoC). Although conventional CNN accelerators can reduce the computational time of learning and inference tasks, they tend to occupy large chip areas due to many multiply-and-accumulate (MAC) operators when implemented in complex digital circuits, incurring excessive power consumption. To overcome these drawbacks, this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter (ADC). This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips. ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory. This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register (SAR) ADC. Unlink most other SAR-ADCs with differential structure; the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption. The SAR ADC implementation also introduces a unique circuit that reduces kick-back noise to increase performance. It was implemented in a test chip using a 55 nm CMOS process. It demonstrates that the proposed ADC reduces Kick-back noise by 40% and consequently improves the ADC’s resolution by about 10% while providing a near rail-to-rail dynamic range with significantly lower power consumption than conventional ADCs. The ADC test chip shows a chip size of 4600 μm² with a power consumption of 6.6 μW while providing an signal-to-noise-and-distortion ratio (SNDR) of 68.45 dB, corresponding to an effective number of bits (ENOB) of 11.07 bits.

Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM

In the design of nonvolatile memory (NVM), the sense amplifier (SA) contributes a major part of the power consumption due to high-frequency read operations. This brief proposes a leakage-current-canceling current-sampling sense amplifier (LCCS-SA) for the suppression of the read power consumption by operating in near-threshold region. The proposed LCCS-SA adopts the technology of offset cancellation and single-ended differential circuit structure to compensate the effect of the leakage current. The bit-line (BL) leakage-induced read failure is effectively suppressed in near-threshold region. Monte Carlo simulation demonstrates that the proposed LCCS-SA can operate at a supply voltage of 0.4 V and achieves 4.4 times lower read energy per bit compared to the conventional current-sampling-based SA.

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field-programmable gate array, is proposed for an energy-efficient yet high-performance binarized convolutional neural network (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45 nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional NV-LUT circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of the energy consumption of a BCNN accelerator for digit recognition compared to that of a conventional SRAM-LUT-based implementation.

A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators

This brief presents a high-resolution ADC which makes use of the pseudo-pseudo-differential noise filtering technique in an oversampling ADC architecture with ring amplifier based integrators. The pseudo-pseudo-differential noise filtering technique utilizes single-ended circuits while maintaining the even-order rejection found in fully-differential structures which alleviates, in the active analog blocks, the need for differential matching and circuit overhead such as common-mode feedback. Additionally, pseudo-pseudo-differential provides a cancellation of low frequency flicker noise without the need for traditional techniques such as auto-zero, correlated-double-sampling, or chopping and mitigates double-sampling thermal noise penalties by processing input signal twice. In this prototype, the flicker corner is maintained below 50Hz with measured ADC performance achieving a peak SNDR of 105.0dB and a dynamic range of 106.5dB while consuming 1.17mW from a 1.8V supply.

Tunable Balanced Power Dividers: An Overview of Recently Developed Balanced Power Dividers and Couplers With Fixed and Tunable Functions

Signal crosstalk and common-mode noise are two issues for engineers when designing today's increasingly complicated microwave integrated circuits [1]. Compared with single-ended circuits, balanced circuits can provide high immunity to environmental noise and broadband common-mode rejection capability [2]. Over the past few years, various balanced passive circuits, such as filters [3], antennas [4], power dividers, and couplers [5]-[17], have been extensively studied. Power dividers and couplers are widely used in microwave integrated circuits, such as antenna feeding networks, balanced mixers, and amplifiers. Balanced couplers are used in double-balanced mixers [18] and balanced frequency doublers [19] to achieve higher efficiency and lower loss.

Balanced to Unbalanced: An Overview of Multifunctional Wideband Balanced-to-Unbalanced Four- and Five-Port Filtering Power Dividers

Fifth-generation (5G) communication techniques are growing in popularity, and 5G will become the commercial operation standard for mainland China in 2020 [1]. As the next-generation mobile communication network, 5G will not only greatly improve communication efficiency; it will also change the way people live and work. The 5G communication system contains the millimeter-wave and sub-6-GHz bands. For the sub-6-GHz band, circuits are becoming ever more compact and multifunction; thus, electromagnetic interference and multicoupling problems will greatly affect the entire system's performance [2]-[4]. In response, balanced circuits with higher immunity to environmental noises [5]-[8], lower electromagnetic interference [9]-[11], and better dynamic range [12]-[15] have attracted increasing attention in the past few years, and a large number of balanced circuits are being conceived [16], [17]. Currently, all feature differential-mode input and output terminals, so they cannot be connected directly to single-ended circuits. Balanced filters, antennas, and power dividers that can be cointegrated with balanced active circuits are required for the development of fully balanced transmitter and receiver RF chains, such as the balanced power dividers that can be connected to a Doherty power amplifier in a balanced system. In this case, balancing is only necessary at the input and output stages. It is expected that the transistor stage is still a single-ended structure, where only two amplifier devices are needed [18].

Differentially Fed Dielectric Resonators: Applications in Filters and Antennas

With the rapid development of wireless communication technology, high-performance miniaturized RF circuits are becoming more complicated, and more functions and signals are being packed into a small, tight space, resulting in a significant level of electromagnetic (EM) interference and signal crosstalk. In modern wireless communication systems, a higher signal-to-noise ratio is desirable and can be attained using differential signals and circuits. Using the differential technique, commonmode (CM) interference is rejected, enhancing signal transparency. Thus, lots of attention has been drawn to differential/balanced circuits, owing to their advantages over traditional single-ended circuits, such as immunity to interference, high reliability, considerable output power, harmonic suppression, and so on [1]. Corresponding to this trend, differential topologies have been used to design basic and key devices for RF front-end systems, such as filters [2], [3], power dividers [4], antennas [5], [6], and active components [7].

Closed-Loop Gate Drive for Single-Ended Forward Converter to Reduce Conducted EMI

Forward DC/DC converters are widely used in low and medium power circuits that are widely used in the aerospace and navigation fields. Power converters are usually sources of electromagnetic interference (EMI), which is due to their higher voltage and current transients. The traditional method is to add expensive filters on the primary side or the secondary side, but its disadvantages are high cost and poor adjustability. Based on the principle that the greater the number of derivations of voltage transients, the lower the high frequency electromagnetic interference contained in this voltage, a signal containing small high-frequency noise that is suitable for the hardware circuit as a reference signal is selected, and a closed-loop gate drive method is used in this paper, which attenuate the conducted EMI noise in the input bus of the forward DC/DC converter. The reference signal shapes the output signal to achieve the purpose of suppressing electromagnetic interference through the closed loop circuit. The advantages of this method are making the output highly adjustable, reducing hardware size and weight and lower cost compared with filter method. Compared with the method of controlling current to reduce electromagnetic interference, the proposed method is easier to implement. Firstly, the relationship between the derivative order of voltage transient and electromagnetic interference is introduced. Secondly, the experimental principle of single-ended forward circuit controlled by closed loop is introduced. Simulation and experimental results show that the proposed method can achieve voltage shaping and suppression of voltage overshoot effectively. Compared with the traditional hard-switching control method, the proposed method can make the high-frequency components of the drain-source voltage of the primary-side MOS transistor and the secondary-side output voltage have a greater attenuation.

Reflectionless Filters for Generalized Elliptic Transmission Functions

Single-ended circuit topologies, and a theorem for the development thereof, are presented with which one may realize constant-resistance (or reflectionless) filters, having ideally zero reflection coefficient at all frequencies and from all ports, suitable for elliptic and pseudo-elliptic filter responses. The proposed theorem produces topologies of a type known as the coupled-ladder, which has been previously studied for only polynomial responses (e.g. Butterworth, Chebyshev, etc.). A comparison between these topologies and another classical approach known as the economy bridge reveals that those proposed here have a number of theoretical and practical advantages. The theory is tested by the construction of a sixth-order, low-pass reflectionless filter exhibiting a pseudo-elliptic frequency response. Measured results are in excellent agreement with theory, and show return loss better than 20 dB throughout the pass-band, the transition-band, and up to two octaves into the stop-band.

Prototype single-ended and pseudo-differential charge processing circuit for micro-strip silicon and gaseous sensors read-out

Detector read-out electronics for Physics Experiments as for example Compressed Baryonic Matter experiment at FAIR, Darmstadt, Germany, should meet tight requirements concerning noise (ENC < 1000 e− rms to guarantee event reconstruction), power consumption (< 10 mW/channel) and average input hit frequency of 250 kHit/s/channel. The ICs design should take into account not only the charge processing parameters but also the impact of the environmental and system-level conditions like radiation, noisy power supply, and temperature to ensure reliable and stable operation during an experiment in a system built with tens of thousands of devices. The operation with gaseous detectors requires particularly effective protection of the inputs against electrostatic discharge. The ESD protection circuit (in particular based on MOS transistors), together with the sensor itself, or AC-coupling capacitors (after irradiation) can be however a source of additional leakage current flowing into the first stage of charge processing chain and affecting the performance. The read-out electronics (in particular first stage—charge sensitive amplifier, CSA) and detector-related noise can be mitigated using proper filtration and signal shaping. However, noise introduced by external sources, like power supply interference, can not be limited only via proper shaping and filtration. When LC filtering is not possible (due to high magnetic fields), it may be beneficial to use differential or pseudo-differential signal processing. The purpose of this work was to test several ideas to improve noise performance and to make the architecture of charge processing chain configurable to better adapt to different target radiation imaging applications. The ASIC comprises four single-ended and four pseudo-differential signal processing channels. In both types of channels configurable slow shaper configuration is used—it is switchable CR-RC2 type shaper and complex conjugate poles 3rd order shaper. CSA feedback in single-ended architecture can be selected between MOS transistor working in a linear region and double-polarity Krummenacher circuit for leakage current compensation capability. The chip was designed and fabricated in Q4 2018 using 180 nm process. Front-end single-ended and differential channels occupy the area from 950 × 60 μm2 up to 1150 × 125 μm2 and consume 5 mW up to 12 mW of power respectively. The work presents design and measurements results.

A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolutetemperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Qfactor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 ㎓ under typical corner conditions (tt, 1.2V, 27 ℃). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.

Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications where usually differential structures are needed. In most cases, the resulting single-ended circuit will be much simpler than the fully or pseudo-differential one. It does not require common-mode feedback circuitry, nor single-ended-to-differential and differential-to-single-ended conversions at the input and output ports. The amplifiers may be single-ended, using, e.g., inverter-based circuits, and the use of baluns can be avoided. The number of pins and pads of the chip can be reduced. In addition, the single-ended opamps of the circuit may require less power than differential ones. These factors and the omission of the common-mode feedback circuits as well as the single-ended/differential converters will usually allow significant power savings.

Decoupling Structures for Millimeter Wave Integrated Circuits in Digital CMOS Processes

This brief studies the effect of nonideal decoupling structures on the performance of single-ended circuits operating at the millimeter wave frequency range. Based on a first-order approximation, an upper limit on the impedance of decoupling structures is derived, given a prespecified accepted degradation in insertion loss. To verify the analysis, a 110-GHz single-ended amplifier with a compact decoupling structure based on distributed interdigitized metal-oxide-metal capacitor is implemented. The full-wave electromagnetic simulations of the decoupling structure show an input impedance of (0.47 – j0.12) $\Omega $ at 110 GHz, and the magnitude is less than $1~\Omega $ from 82 to 144 GHz. The degradation in the insertion loss of the matching network is simulated to be less than 0.5-dB compared with the use of ideal decoupling capacitors at 110 GHz. The area of the decoupling structure is $18\times 100 ~\mu \text{m}^{2}$ when implemented in 65-nm digital CMOS process.

Design of a variation‐resilient single‐ended non‐volatile six‐input lookup table circuit with a redundant‐magnetic tunnel junction‐based active load for smart Internet‐of‐things applications

A variation-resilient single-ended six-input lookup table circuit, which makes it possible to implement any arbitrary six-input logic gates, is proposed. Since operating point is optimally tuned by the redundant magnetic tunnel junction devices after chip fabrication, adequate p-channel metal-oxide semiconductor (PMOS) feedback can be performed, which results in variation-resilient, energy-efficient operation. In fact, the energy consumption of the proposed circuit is 66% smaller than that of the conventional single-ended circuit.

An isolated AC module for photovoltaic energy conversion

ABSTRACTIn this paper, an isolated ac module with pseudo dc-link and galvanic isolation is proposed for photovoltaic energy conversion. The studied grid-tie ac module can individually extract the maximum solar power from each photovoltaic panel and transfer to ac utility system. It consists of an interleaved active-clamping single-ended primary-inductive circuit (SEPIC) with a secondary voltage doubler, a full-bridge polarity selector operating under line frequency to achieve high efficiency. For the studied topology, key features such as reduced input current ripple, zero-voltage switching (ZVS) of primary switches, low reverse-recovery current of the output diodes, and lower switch voltage stress are obtained. Also, to reduce input current ripple, an interleaved control strategy is adopted. A simple control strategy is proposed to generate a rectified sinusoidal waveform voltage at the pseudo dc-link capacitors and achieve the high maximum power point tracking (MPPT) accuracy. The operation principles and design considerations of the studied ac module are analyzed and discussed. A prototype with 25–60 V dc input, 110 V/60 Hz ac output and 150 W power rating has been constructed for verifying the feasibility of the proposed ac module.

A Stabilization Technique for Single-Ended and Differential Harmonic Oscillators

A stabilization technique is presented for harmonic oscillators which can reduce deviation of radio-frequency parameters against process variation. The stabilizing gate circuit (SGC) is designed to improve fidelity of oscillation amplitude, phase noise, and period jitter without a significant increase in power requirement. Process-related phenomena such as device aging, feature size uncertainty, and supply ripples are covered through modeling of threshold voltage, device dimension, and power rail variation. Single-ended and differential circuits of inductor-capacitor (LC)- tuned Hartley harmonic oscillators are simulated with 90-nm device parameters to verify the SGC's effectiveness for diverse front ends. The technique is able to reduce variability of phase noise and period jitter by up to 34 dBc/Hz and 76 fs over a wide range of offset frequencies (10$$^3$$3---10$$^6$$6 Hz). It also improves stability of oscillation amplitude by up to 29 % and performs better than other reported process compensation mechanisms.

Digital bilinear feedback for low‐power double‐sampling sigma–delta modulators

A novel double-sampling (DS) technique for use in sigma–delta modulators (ΣΔMs) is presented. The proposed technique uses a digital bilinear filter in the feedback path of the modulator loop. The bilinear filter suppresses the quantisation noise folding (QNF) that results from the DS path mismatch. Unlike other solutions for the QNF, the digital implementation of this filter allows the sharing of the input sampling capacitor with the feedback sampling capacitor without any additional analogue gain stages. This way, the power consumption in the input signal buffer can be greatly reduced, because it benefits from the nullator effect at the input of the ΣΔM loop, and hence the current needed to drive the shared sampling capacitor is drastically reduced. Moreover, the proposed DS technique is also suitable for a single-ended circuit implementation of DS.

Designing nonlinearity characterization for mixed-signal circuits in system-on-chip

Long test times and the use of conventional automatic test equipment (ATE) makes conventional mixed-signal linearity performance testing costly. Diminishing test time of linearity test significantly reduces system-on-a-chip production test costs and, therefore, lessens total product manufacturing costs. Several low-cost linearity test methods have addressed this issue for a single-ended mixed-signal circuit testing. On the other hand, a low-cost test approach has rarely been proposed for differential mixed-signal circuits, due to a new class of test obstacles from differential circuits that are widely employed for high-speed I/O products. This paper presents a cost-effective self-test methodology to characterize the linearity performance of differential mixed-signal circuits in loopback mode. The proposed method precisely predicts the device-under-test (DUT) linearity specifications by building accurate DUT nonlinear polynomial models using spectral specifications from recent work. The test cost is significantly reduced by replacing conventional ATE with the proposed self-test platform and by reducing test time to a fraction of conventional testing time. Hardware measurement results validated the test performance of the proposed test scheme.