Prototype single-ended and pseudo-differential charge processing circuit for micro-strip silicon and gaseous sensors read-out

Abstract

Detector read-out electronics for Physics Experiments as for example Compressed Baryonic Matter experiment at FAIR, Darmstadt, Germany, should meet tight requirements concerning noise (ENC < 1000 e− rms to guarantee event reconstruction), power consumption (< 10 mW/channel) and average input hit frequency of 250 kHit/s/channel. The ICs design should take into account not only the charge processing parameters but also the impact of the environmental and system-level conditions like radiation, noisy power supply, and temperature to ensure reliable and stable operation during an experiment in a system built with tens of thousands of devices. The operation with gaseous detectors requires particularly effective protection of the inputs against electrostatic discharge. The ESD protection circuit (in particular based on MOS transistors), together with the sensor itself, or AC-coupling capacitors (after irradiation) can be however a source of additional leakage current flowing into the first stage of charge processing chain and affecting the performance. The read-out electronics (in particular first stage—charge sensitive amplifier, CSA) and detector-related noise can be mitigated using proper filtration and signal shaping. However, noise introduced by external sources, like power supply interference, can not be limited only via proper shaping and filtration. When LC filtering is not possible (due to high magnetic fields), it may be beneficial to use differential or pseudo-differential signal processing. The purpose of this work was to test several ideas to improve noise performance and to make the architecture of charge processing chain configurable to better adapt to different target radiation imaging applications. The ASIC comprises four single-ended and four pseudo-differential signal processing channels. In both types of channels configurable slow shaper configuration is used—it is switchable CR-RC2 type shaper and complex conjugate poles 3rd order shaper. CSA feedback in single-ended architecture can be selected between MOS transistor working in a linear region and double-polarity Krummenacher circuit for leakage current compensation capability. The chip was designed and fabricated in Q4 2018 using 180 nm process. Front-end single-ended and differential channels occupy the area from 950 × 60 μm2 up to 1150 × 125 μm2 and consume 5 mW up to 12 mW of power respectively. The work presents design and measurements results.