A Stabilization Technique for Single-Ended and Differential Harmonic Oscillators

Abstract

A stabilization technique is presented for harmonic oscillators which can reduce deviation of radio-frequency parameters against process variation. The stabilizing gate circuit (SGC) is designed to improve fidelity of oscillation amplitude, phase noise, and period jitter without a significant increase in power requirement. Process-related phenomena such as device aging, feature size uncertainty, and supply ripples are covered through modeling of threshold voltage, device dimension, and power rail variation. Single-ended and differential circuits of inductor-capacitor (LC)- tuned Hartley harmonic oscillators are simulated with 90-nm device parameters to verify the SGC's effectiveness for diverse front ends. The technique is able to reduce variability of phase noise and period jitter by up to 34 dBc/Hz and 76 fs over a wide range of offset frequencies (10$$^3$$3---10$$^6$$6 Hz). It also improves stability of oscillation amplitude by up to 29 % and performs better than other reported process compensation mechanisms.