Single-ended Circuit Research Articles

Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique.

Microwave mixers employing multiple-barrier semiconductor heterostructure devices

Experimental data on mixer performance of unipolar semiconductor heterostructure diodes containing bulk alloy-ramp barriers are presented. Prototype Al/sub x/Ga/sub 1-x/As/GaAs heterostructures containing one, two, and four barriers are fabricated by MBE and tested in a single-ended mixer circuit at 10 GHz. The devices with two and four barriers, which exhibit improved performance over the single-barrier device, achieve conversion losses between 4 and 6 dB and noise temperature ratios between 1.5 and 2 at 300 K. Several significant advantages over contending Schottky diodes are also discussed. The results indicate that multiple-barrier devices are good candidates for use in microwave and millimeter-wave mixer circuits. >

Maximizing the signal-to-noise ratio of the electromagnetic seismometer: The optimum coil resistance, amplifier characteristics, and circuit

AbstractThis study finds the optimum coil resistance, rc.opt, which maximizes the signal-to-noise ratio (SNR) of an electromagnetic (EM) seismometer and amplifier combination. The optimum coil resistance is shown to be the product of a seismometer factor (SF) times the noise resistance, Rn, of the amplifier. The seismometer factors range from 1.13 to 3.66 for the nine EM seismometers considered. The minimum noise figure solution, in which the amplifier noise resistance is set equal to the coil resistance, is shown to correspond to the special case in which there is no damping resistor present. It is also shown that the optimum form for the noise resistance is a constant independent of frequency and that this feature can be approximated with FET-like components such as the MAT-02. Examples of using rc.opt are given using both the 5500-ohm and the 500-ohm 1-Hz L4-C seismometers paired with the OP-27 and LT1028 operational amplifiers, respectively. It is pointed out that, although the resulting amplitude signal-to-noise ratios (ASNRs) are approximately equal, it is best to choose the seismometer-amplifier pair having the larger generator constant because it results in a larger signal. Furthermore, if the coil resistance is not the optimum value, the resulting decrease in the ASNR is less if the coil resistance is chosen greater than the optimum rather than less.The deleterious effects of mismatching seismometer and amplifier are shown by comparing ASNRs for the GS-13 seismometer paired with three different amplifiers. The degradation in ASNR is found to be as large as a factor of 3. It is pointed out that mismatching would not be done purposely but can inadvertently occur when connecting an EM seismometer to a seismic recorder whose input noise resistance properties are unknown, as in generally the case. It is recommended that manufacturers of seismic recorders obtain the necessary input noise data from the component manufacturers and supply the input noise resistance to users.Finally, the three commonly used single-ended preamplifier circuits used for EM seismometers are compared in terms of their resulting ASNRs. The same seismometer and amplifier are used in all three circuits. For the GS-13/MAT-02 pair, the noninverting, parallel damping resistor circuit resulted in an ASNR that was 3.8 times larger than that for the inverting, parallel damping resistor circuit, and 3 times larger than that for the inverting, series damping resistor circuit.

Performance analysis and circuit design of high-frequency resonant inverter using a single reverse-conducting device

This paper is concerned mainly with a performance analysis and a design method of a newly developed zero-current switching quasi-resonant high-frequency inverter (ZCS-QRI) using a single reverse-blocking power device (high-frequency GATT). As a matter of fact, GATT is replaced by the latest MOS-gate power semiconductor devices, MOSFET, IGBT, MCT and Bi-MOS · GTO thyristor. The frequency-modulated single-ended inverter circuit, which incorporates an auxiliary diode and large reactor cascade branch in parallel with a resonant capacitor connected into the transformer-link series-resonant tuned tank load circuit can stably and efficiently operate in the frequency range from 20 kHz up to 50 kHz or so. It is proved that the ZCS-QRI is more suitable for several kilowatt induction-heating and melting power supplies and high-intensity ultrasonic generator, and switched-mode dc-dc converters. This simple high-frequency ZCS-QRI for induction-heating load model is analyzed introducing normalized resonant and load circuit parameters and control variable on the basis of computer-aided simulation. The load and frequency regulation characteristics of ZCS-QRI and ZCS operating range are illustrated with a normalized expression in addition to voltage and current peak values and stresses of the power semiconductor device. The practical computer-aided design procedure using the inverter characteristics in steady-state expressed in the normalized technique is demonstrated and discussed including a design example. The simulation results of ZCS-QRI are illustrated and compared with the experimental results in trial-produced breadboard.

Performance Analysis and circuit Design of High-Frequency Resonant Inverter using a Single Reverse-Conducting Device.

This paper is mainly concerned with a performance analysis and a design method of a newly-developed zero-current switching quasi-resonant high frequency inverter (ZCS-QRI) using a single reverse-blocking power device (high-frequency GATT). As a matter of fact, GATT is replaced by the latest MOS-gate power semiconductor devices, MOSFET, IGBT, MCT and Bi-MOSGTO Thyristor.The frequency-modulated single-ended inverter circuit, which incorporates an auxiliary diode & large reactor cascade branch in parallel with a resonant capacitor connected into the transformerlink series-resonant tuned tank load circuit can stably and efficiently operate in the frequency range from 20kHz up to 50kHz or so. It is proved that the ZCS-QRI is more suitable for several kW induction-heating and-melting power supplies and high-intensity ultrasonic generator, and switched-mode DC-DC converters.This simple high-frequency ZCS-QRI for induction-heating load model is analyzed introducing normalized resonant and load circuit parameters and control variable on the basis of the computeraided simulation. The load and frequency regulation characteristics of ZCS-QRI and ZCS operation range are illustrated with a normalized expression in addition to voltage and current peak values and stresses of the power semiconductor device. The practical computer-aided design procedure using the inverter characteristics in steady-state expressed in the normalized technique is demonstrated and discussed including a design example. The simulation results of ZCS-QRI are illustrated and compared with the experimental results in trially-produced breadboard.

Bandpass sigma-delta analog-to-digital conversion

The traditional low-pass sigma-delta ( Sigma Delta ) analog-to-digital converter is extended to the bandpass case. For input signals with small relative bandwidths, bandpass Sigma Delta converters offer high signal-to-noise ratios at significantly lower sampling rates than are required for low-pass Sigma Delta converters. A sixth-order single-ended switched-capacitor circuit, clocked at 3 MHz, is designed to convert bandpass signals centered at 455 kHz with 20-kHz bandwidth. Time-domain circuit simulations show that this modulator realizes a 94-dB signal-to-noise ratio for a half-scale input, giving roughly 16-b performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

43-ps 5.2-GHz macrocell array LSIs

A family of bipolar macrocell array LSIs has been developed which has a basic delay of 43 ps/CML and a toggle frequency of 5.2 GHz/flip-flop. This family uses a cascaded-differential and single-ended CML circuit and a highly advanced super self-aligned process technology (SST-1B) which uses a selectively ion-implanted collector technology based on SST-1A. Using the macrocell array LSIs, performances of 1.2 ns/1.2 W for a 6-bit multiplier, and 4.3 ns/3 W for a 16-bit multiplier have been achieved. >

Level-shifting differential to single-ended convertor circuits GaAs MESFET implementation

The letter describes three possible circuits for performing differential to single-ended conversion using gallium arsenide technology, and compares them by analysis confirmed by computer simulation. The circuits can be used to provide a differential input for single-input high-performance gallium arsenide operational amplifiers.

Erratum: Floating integrator technique for switched-capacitor circuits employing reset cycles

A simple `floating? integrator technique is presented that is applicable to both single-ended and differential switched-capacitor circuits which employ reset cycles. This method is useful in eliminating the effects of any input offset or interstage differential or common-mode offsets in DC-coupled circuits. A monolithic circuit is demonstrated which uses this technique to achieve accurate differential integration of low-level signals in the presence of substantial differential and common-mode input offsets.

Floating integrator technique for switched-capacitor circuits employing reset cycles

A simple ‘floating’ integrator technique is presented that is applicable to both single-ended and differential switched-capacitor circuits which employ reset cycles. This method is useful in eliminating the effects of any input offset or interstage differential or common-mode offsets in DC-coupled circuits. A monolithic circuit is demonstrated which uses this technique to achieve accurate differential integration of low-level signals in the presence of substantial differential and common-mode input offsets.

Differential-feedback magnetic amplifiers

In push-pull TYPE magnetic amplifiers with two single-ended external-feedback or self-saturating circuits in back-to-back connection, each of these circuits has its own positive-feedback component which reduces or nearly nullifies the intrinsic negative feedback of the ordinary saturable reactor (transductor). As a result of this fact, the individual quiescent currents of these circuits vary considerably with large changes in supply voltage, frequency, and ambient temperature. Therefore, the characteristics of the magnetic-core and rectifier elements have to be carefully matched over a large part of the working range to avoid excessive asymmetry zero-drift errors. This necessity becomes particularly important in low-level d-c signal applications in the realm of instrumentation, control engineering, and analog computer technique.