Single-electron Transistor Research Articles

Room-temperature single-electron tunneling in highly-doped silicon-on-insulator nanoscale field-effect transistors

From the viewpoint of high- (room-) temperature operation of donor-based single-electron transistors, we make a comparative study of nano-scale silicon-on-insulator transistors with phosphorus-doped channels for two dopant-concentration regimes: N D ≈ 1 × 1018 and 2 × 1020 cm−3. We experimentally show that the high-N D devices can provide room-temperature single-electron tunneling operation owing to a large tunnel-barrier height, while operation temperature is limited to about 100 K for the low-N D devices. Numerical simulations of random donor-atom distributions indicate that donor clustering plays a dominant role in the formation of quantum dots, and suggests that clusters comprising of more-than-three donors are responsible for room-temperature operation.

Single charge transport in a fully superconducting SQUISET locally tuned by self-inductance effects

We present a single-electron device for the manipulation of charge states via quantum interference in nanostructured electrodes. Via self-inductance effects, we induce two independent magnetic fluxes in the electrodes and we demonstrate sensitivity to single charge states and magnetic field at variable temperature. Moreover, our approach allows us to demonstrate local and independent control of the single-particle conductance between nano-engineered tunnel junctions in a fully superconducting quantum interference single-electron transistor, thereby increasing the flexibility of our single-electron transistors. Our devices show a robust modulation of the current-to-flux transfer function via control currents while exploiting the single-electron filling of a mesoscopic superconducting island. Further applications of the device concept to single charge manipulation and magnetic-flux sensing are also discussed.

Correlated Hofstadter spectrum and flavour phase diagram in magic-angle twisted bilayer graphene

In magic angle twisted bilayer graphene (MATBG), the moir\'e superlattice potential gives rise to narrow electronic bands1 which support a multitude of many-body quantum phases. Further richness arises in the presence of a perpendicular magnetic field, where the interplay between moir\'e and magnetic length scales leads to fractal Hofstadter subbands. In this strongly correlated Hofstadter platform, multiple experiments have identified gapped topological and correlated states, but little is known about the phase transitions between them in the intervening compressible regimes. Here, using a scanning single-electron transistor microscope to measure local electronic compressibility, we simultaneously unveil novel sequences of broken-symmetry Chern insulators (CIs) and resolve sharp phase transitions between competing states with different topological quantum numbers and spin/valley flavor occupations. Our measurements provide a complete experimental mapping of the energy spectrum and thermodynamic phase diagram of interacting Hofstadter subbands in MATBG. In addition, we observe full lifting of the degeneracy of the zeroth Landau levels (zLLs) together with level crossings, indicating moir\'e valley splitting. We propose a unified flavor polarization mechanism to understand the intricate interplay of topology, interactions, and symmetry breaking as a function of density and applied magnetic field in this system.

Transfer Characteristics Analysis of Single Electron Transistor

Single Electron Transistor is often referred to as a nanometer scale because it can be made very small and can detect the movement of individual electrons. However, the SET has a high input impedance, low voltage gain, and is sensitive to random background charges. The Transfer characteristics features of a SET are calculated by analyzing the different resistance of the tunnels and the tunneling capacitance. Tunneling method is considering a stochastic process, and the state master equation is solving to calculate the free energy change. There are some unusual variations that set the limit for parallel circuit parameters for proper operation. The SET can maintain its scalability and control the movement of individual electrons. In this paper, we have provided a comparative and simulated study of standard CMOS device, SET and hybrid circuits such as a switched capacitor filter.

Spin-orbit coupling effects on thermoelectric transport properties in quantum dots

We study the effects caused by Rashba and Dresselhaus spin-orbit coupling over the thermoelectric transport properties of a single-electron transistor, viz., a quantum dot connected to one-dimensional leads. Using linear response theory and employing the numerical renormalization group method, we calculate the thermopower, electrical and thermal conductances, dimensionless thermoelectric figure of merit, and study the Wiedemann-Franz law, showing their temperature maps. Our results for all those properties indicate that spin-orbit coupling drives the system into the Kondo regime. We show that the thermoelectric transport properties, in the presence of spin-orbit coupling, obey the expected universality of the Kondo strong coupling fixed point. In addition, our results show a notable increase in the thermoelectric figure of merit, caused by the spin-orbit coupling in the one-dimensional quantum dot leads.

SEBAT-Based Readout for FET THz Detectors With Intrinsic Power-to-Frequency Conversion

TeraHertz (THz) detection with Field-Effect Transistor-based (FET-based) detectors requires low-noise amplification, which typically involves trade-offs in terms of complexity, power, and area, resulting in severe scalability constraints for pixel integration into imaging arrays. The purpose of this paper is to describe a novel approach, from design to experimental validation, that enables active device-level amplification of the signal generated by a FET detector and converts it to a frequency suitable for digital processing. This has been done by exploiting a Single-Electron Bipolar Avalanche Transistor (SEBAT) to build a low-noise compact front-end circuit. The FET output is connected to the SEBAT forming a circuit element that here is defined as a TeraHertz Single-Electron Transistor (THzSET). The FET generates a detection current when it senses the THz signal; this current is then injected into the SEBAT, which generates an avalanche current pulse for each single electron, achieving a device-level amplification. The avalanche pulse rate is then evaluated from the signal measured at the SEBAT collector, and performing an FFT of the counts-per-second curve over time it is possible to measure the modulated THz signal applied to the device. The obtained Responsivity <inline-formula> <tex-math notation="LaTeX">$\text {R}_{\text {F}}$ </tex-math></inline-formula> and the Noise Equivalent Power NEP are respectively <inline-formula> <tex-math notation="LaTeX">$\frac {\text {4.61Gcps}}{\text {W}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\frac {\text {88nW}}{\sqrt {\text {Hz}}} $ </tex-math></inline-formula> at 330GHz illumination frequency. This is achieved with sub-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power consumption and minimal area overhead: indeed, the pixel and the interface have a total area of 0.146mm², where the antenna area is <inline-formula> <tex-math notation="LaTeX">${455} \times {320}\mu \text{m}^{{2}}$ </tex-math></inline-formula> and the SEBAT area is <inline-formula> <tex-math notation="LaTeX">${27} \times {22}\mu \text{m}^{{2}}$ </tex-math></inline-formula>.

High-frequency rectifying characteristics of metallic single-electron transistor with niobium nanodots

Metallic single-electron transistors (SETs) with Nb nanodots were fabricated and their high-frequency rectifying characteristics were evaluated. By reducing the gap size of the electrodes and film deposition area to nanometer scale, improved SET characteristics with gate control and better frequency response of the rectifying current with gentler decrease than 1/f at high frequency were achieved. A comparison between the characteristics of micrometer- and nanometer-size devices is made, and the reasons for their differences are discussed with the aid of simulations based on the experimentally extracted parameters.

Reduced Electron Temperature in Silicon Multi-Quantum-Dot Single-Electron Tunneling Devices.

The high-performance room-temperature-operating Si single-electron transistors (SETs) were devised in the form of the multiple quantum-dot (MQD) multiple tunnel junction (MTJ) system. The key device architecture of the Si MQD MTJ system was self-formed along the volumetrically undulated [110] Si nanowire that was fabricated by isotropic wet etching and subsequent oxidation of the e-beam-lithographically patterned [110] Si nanowire. The strong subband modulation in the volumetrically undulated [110] Si nanowire could create both the large quantum level spacings and the high tunnel barriers in the Si MQD MTJ system. Such a device scheme can not only decrease the cotunneling effect, but also reduce the effective electron temperature. These eventually led to the energetic stability for both the Coulomb blockade and the negative differential conductance characteristics at room temperature. The results suggest that the present device scheme (i.e., [110] Si MQD MTJ) holds great promise for the room-temperature demonstration of the high-performance Si SETs.

Effect of elastic disorder on single-electron transport through a buckled nanotube

We study transport properties of a single electron transistor based on elastic nanotube. Assuming that an external compressive force is applied to the nanotube, we focus on the vicinity of the Euler buckling instability. We demonstrate that in this regime the transport through the transistor is extremely sensitive to elastic disorder. In particular, built-in curvature (random or regular) leads to the ``elastic curvature blockade'': appearance of threshold bias voltage in the $I$-$V$ curve which can be larger than the Coulomb-blockade-induced one. In the case of a random curvature, an additional plateau in dependence of the average current on a bias voltage appears.

An electron turnstile for frequency-to-power conversion.

Single-electron transport relates an operation frequency f to the emitted current I through the electron charge e as I = ef (refs. 1-5). Similarly, direct frequency-to-power conversion (FPC) links both quantities through a known energy. FPC is a natural candidate for a power standard resorting to the most basic definition of the watt: energy emitted per unit of time. The energy is traceable to Planck's constant and the time is in turn traceable to the unperturbed ground state hyperfine transition frequency of the caesium 133 atom. Hence, FPC comprises a simple and elegant way to realize the watt6. In this spirit, single-photon emission7,8 and detection9 at known rates have been proposed as radiometric standards and experimentally realized10-14. However, power standards are so far only traceable to electrical units, that is, to the volt and the ohm6,15-17. In this Letter, we demonstrate an alternative proposal based on solid-state direct FPC using a hybrid single-electron transistor (SET). The SET injects n (integer) quasi-particles (QPs) per cycle into the two superconducting leads with discrete energies close to their superconducting gap Δ, even at zero source-drain voltage. Furthermore, the application of a bias voltage can vary the distribution of the power among the two leads, allowing for an almost equal power injection nΔf into the two. While in single-electron transport current is related to a fixed universal constant (e), in our approach Δ is a material-dependent quantity. We estimate that under optimized conditions errors can be well below 1%.

Schemes for Single Electron Transistor Based on Double Quantum Dot Islands Utilizing a Graphene Nanoscroll, Carbon Nanotube and Fullerene.

The single electron transistor (SET) is a nanoscale switching device with a simple equivalent circuit. It can work very fast as it is based on the tunneling of single electrons. Its nanostructure contains a quantum dot island whose material impacts on the device operation. Carbon allotropes such as fullerene (C60), carbon nanotubes (CNTs) and graphene nanoscrolls (GNSs) can be utilized as the quantum dot island in SETs. In this study, multiple quantum dot islands such as GNS-CNT and GNS-C60 are utilized in SET devices. The currents of two counterpart devices are modeled and analyzed. The impacts of important parameters such as temperature and applied gate voltage on the current of two SETs are investigated using proposed mathematical models. Moreover, the impacts of CNT length, fullerene diameter, GNS length, and GNS spiral length and number of turns on the SET’s current are explored. Additionally, the Coulomb blockade ranges (CB) of the two SETs are compared. The results reveal that the GNS-CNT SET has a lower Coulomb blockade range and a higher current than the GNS-C60 SET. Their charge stability diagrams indicate that the GNS-CNT SET has smaller Coulomb diamond areas, zero-current regions, and zero-conductance regions than the GNS-C60 SET.

Quantum coulomb blockade phenomena in single-electron transistor based on graphene quantum dot

Graphene quantum dot (GQD) is classified in a quantum-coulomb blockade regime, where both of coulomb interaction and confined energy play a crucial role that affect electron transport through the transistors made of GQD. In this paper, the constant interaction model is employed to calculate the addition charge energy of GQDs. The dependency of addition charge energy on the number of electrons and the GQD’s diameter is studied. Finally, the stability diagram of SET based on GQD is modeled and plotted.

Asymmetric, mixed-valence molecules for spectroscopic readout of quantum-dot cellular automata

Mixed-valence compounds may provide molecular devices for an energy-efficient, low-power, general-purpose computing paradigm known as quantum-dot cellular automata (QCA). Multiple redox centers on mixed-valence molecules provide a system of coupled quantum dots. The configuration of mobile charge on a double-quantum-dot (DQD) molecule encodes a bit of classical information robust at room temperature. When arranged in non-homogeneous patterns (circuits) on a substrate, local Coulomb coupling between molecules enables information processing. While single-electron transistors and single-electron boxes could provide low-temperature solutions for reading the state of a ∼1 nm scale molecule, we propose a room-temperature read-out scheme. Here, DQD molecules are designed with slightly dissimilar quantum dots. Ab initio calculations show that the binary device states of an asymmetric molecule have distinct Raman spectra. Additionally, the dots are similar enough that mobile charge is not trapped on either dot, allowing device switching driven by the charge configuration of a neighbor molecule. A technique such as tip-enhanced Raman spectroscopy could be used to detect the state of a circuit comprised of several QCA molecules.

Parallel Comparator based voltmeter using Single Electron Tunneling Transistor

By manipulating an electron that tunnels the tunnel junction of a single electron transistor, one will be able to reach a standard output logic “1” or logic “0”. The operation of the Single Electron Transistor (SET) is depending upon the bias voltage as well as the input signal(s). By varying the input voltage levels of a SET, the output voltage levels can significantly be changed on the basis of tunneling of an electron whether tunneling happened or not. As our concentration is the measuring of an unknown voltage, we are to implement a voltmeter system to provide a digital output of 3 bits whenever an unknown input voltage is kept in touching in the input terminal. A reference/standard voltage (say 8mV) will be connected in series with eight resistances ( 8 Rs) for the purpose of making a seven threshold voltages, for 7 comparators, in an ascending order of values from ground to reference voltage for seven comparators which are used in this present work. The voltmeter implemented consists of (i) a voltage divider, (ii) a set of seven comparators, (iii) seven Exclusive-OR gates and (iv) three 4-input OR gates. The concepts of implementing “Parallel Comparator based voltmeter” is discussed in two ways (i) by classical block diagram and (ii) using Single electron transistor based circuit. The measuring of an input analog voltage will not be the same as the digital output value. A 3-bit output indicates that the input analog voltage must lie on within a particular small range of voltage. The encoder circuit which is connected to the outputs of the comparators is hard to construct whenever the three terminals output are expressed with the output variables (Wi) of the comparators. For simple and user-friendly circuit, the outputs (Wi) of the comparators are modified to Di variables so as to get the same 3-bit encoder/voltmeter output. For this purpose, 7 extra component called 2-input XORs based on SET are used. Seven such XORs are set, and the output of them are passed to three 4-input OR gates according to the required logic expressions. It is found that all the output data of the voltmeter are coherently matched with the theoretical aspects. Processing delays are found out for all circuits. Power consumptions of all of them are shown in tabular and graphical forms. All the circuit we are intending to make are provided in due places with their logic circuit or simulation set and the simulation results are provided as well. Different truth tables are given for keeping track of whether input-output relationships matches with the theoretical results. We have thought of whether the present work circuits are faster or slower than the circuits of CMOS based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 1×10^(-18) Joules to 22×10^(-18)Joules which is very small amount. All the combinational circuits presented in this work are of SET-based.

Finding out square root of an integer number using Single Electron Transistor

The single-electron transistor (SET) attracts the researchers, scientists or technologists to design and construct large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences in a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. The oscillatory conduction as the function of the variable-multiple /single gate voltage is exhibited by SET. This uncommon characteristic provides the ability of executing the functions of AND, OR, XOR, Inverter and some combinational circuits like multiplexer, subtractor etc. For implementing a square root circuit, SET would be a best candidate to fulfil the requirements. The processing speed of SET based devices will be nearly close to electronic speed. Noise during processing gets ultra-low when the circuits is built with SETs. The square root circuit is presented here for sixteen bit input numbers. The input bit numbers can be increased with the increasing of the depth of the pattern very easily. And this will provide us the greater accuracy about the squared root value. Power consumption in the single electron circuit is low irrespective of bipolar junction transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS) circuits. Reducing the numbers of nodes, the power consumption is reduced.

Model of a single-electron transistor based on endohedral fullerene (Sc3N)@C80

In this work within the framework of the density functional theory and the method of nonequilibrium Green’s functions the dependences of the total energy of molecules C80-SET and (Sc3N)@C80 - SET on their total charge, the dependence of the total energy from the gate voltage and the stability diagram of the single-electron transistor have been determined. It is noted that for transition to switch to on mode (Sc3N)@C80-SET it is necessary to apply the gate voltage in the range from 0.019 ≤ VG ≤ 5.940 with the bias voltage -2.040 ≤ VSD ≤ 2.155 V. Considering that at values of bias voltage equal to –0.381 ≤ VSD ≤ 0.533 V there is no voltage on the substrate (VG = 0 V) and electric current does not flow. It is shown that the total energy at negative values of charge is higher than at positive charges and that the area of the Coulomb rhombus in fullerene with scandium nitride is 5.3 times larger than in “pure” fullerene.

Detecting Air Pollutant Molecules Using Tube-Shaped Single Electron Transistor.

An air pollution detector is proposed based on a tube-shaped single-electron transistor (SET) sensor. By monitoring the flow control component of the detector, each air pollutant molecule can be placed at the center of a SET nanopore and is treated as an island of the SET device in the same framework. Electron transport in the SET was incoherent, and the performances of the SET were sensitive at the single molecule level. Employing first-principles calculations, electronic features of an air pollutant molecule within a tube-shaped SET environment were found to be independent of the molecule rotational orientations with respect to axis of symmetry, unlike the electronic features in a conventional SET environment. Charge stability diagrams of the island molecules were demonstrated to be distinct for each molecule, and thus they can serve as electronic fingerprints for detection. Using the same setup, quantification of the air pollutant can be realized at room temperature as well. The results presented herein may help provide guidance for the identification and quantification of various types of air pollutants at the molecular level by treating the molecule as the island of the SET component in the proposed detector.

Phase-dependent transport in thermally driven superconducting single-electron transistors

We investigate thermally driven transport of heat and charge in a superconducting single-electron transistor by means of a real-time diagrammatic transport theory. Our theoretical approach allows us to account for strong Coulomb interactions and arbitrary nonequilibrium conditions while performing a systematic expansion in the tunnel coupling. We find that a temperature bias across the system gives rise to finite heat and charge currents close to the particle-hole symmetric point which depend both on the gate voltage as well as on the phase difference between the superconducting reservoirs. The finite thermoelectric effect arises due to level renormalization from virtual tunneling processes. Furthermore, we find that the phase bias can give rise to finite charge currents even in the presence of an inversion-symmetric temperature bias.

Electromechanical Characteristics by a Vertical Flip of C70 Fullerene Prolate Spheroid in a Single-Electron Transistor: Hybrid Density Functional Methods.

In this study, the B3LYP hybrid density functional theory was used to investigate the electromechanical characteristics of C70 fullerene with and without point charges to model the effect of the surface of the gate electrode in a C70 single-electron transistor (SET). To understand electron tunneling through C70 fullerene species in a single-C70 transistor, descriptors of geometrical atomic structures and frontier molecular orbitals were analyzed. The findings regarding the node planes of the lowest unoccupied molecular orbitals (LUMOs) of C70 and both the highest occupied molecular orbitals (HOMOs) and the LUMO of the C70 anion suggest that electron tunneling of pristine C70 prolate spheroidal fullerene could be better in the major axis orientation when facing the gate electrode than in the major (longer) axis orientation when facing the Au source and drain electrodes. In addition, we explored the effect on the geometrical atomic structure of C70 by a single-electron addition, in which the maximum change for the distance between two carbon sites of C70 is 0.02 Å.

Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.