VLSI Circuit Simulation Research Articles

Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition

We model the effects of cross-sectional radius scaling on ${C}$ – ${V}$ and ${I}$ – ${V}$ characteristics of gate-all-around FETs (GAAFETs), capturing the continuous transition from a 3-D electron system to a 1-D electron system. We have obtained computationally efficient models for effective mass, bandgap, and subband energies as functions of the cross-sectional radius and gate voltage based on simple approximate analytic expressions. Together, they provide a compact model for VLSI circuit simulation, especially for analog and RF circuits that will be seriously affected by the new humps and peaks in ${C}$ – ${V}$ and ${I}$ – ${V}$ introduced by the subbands. The model has been validated with ${k}\cdot {p}$ -based technology computer aided design simulations as well as measured data. To the best of our knowledge, this is the first compact model capturing cross-sectional size-dependent dimensional crossover (3-D to 1-D) in ${I}$ – ${V}$ and ${C}$ – ${V}$ for GAAFETs.

Structure-Preserving-Based Model-Order Reduction of Parameterized Interconnect Systems

In recent years, the continued miniaturization of VLSI circuits leads to the need for more efficient simulation of large-scale linear dynamical systems with ever-increasing state-space dimension. The linear dynamical systems in VLSI circuit simulation are RC or RCL models of the VLSI circuit’s interconnected system. Model-order reduction is an important technique to reduce such a high complexity. Along the technology scaling, the indetermination in the manufacturing process causes variations in the critical dimensions and interlevel dielectric thickness of interconnects, which could make the system performance unpredictable and produce a significant parametric yield loss. An efficient exploitation of these design activities results in a parameterized model-order reduction technique able to reduce large systems of equations with respect to all of the variable parameters of the circuit, (i.e., resistance, capacitance, and inductance). For this purpose, we propose a novel parameterized model-order reduction method for interconnect variation systems, which is based on an efficient and reliable combination of invariable structure-preserving model-order reduction (SPMOR) methods and variable parameter retaining schemes. It is referred to as a parameterized interconnect model-order reduction via structure-preserving algorithm. The SPMOR model yields the same form of the original state equation and preserves the passivity of the parameterized RC and RLC networks, like the well-known passive reduced-order interconnect algorithm for nonparameterized RC and RLC networks. The most important benefit it entails is the ability to preserve the probability characteristic of the original interconnect systems. Pertinent numerical examples are proposed to validate the proposed SPMOR approach.

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

BSIM5: An advanced charge-based MOSFET model for nanoscale VLSI circuit simulation

This paper outlines the charge-based core and the model architecture of the BSIM5, an advanced charge-based MOSFET model for nanoscale VLSI circuit simulation. Compared with the previous charge-based models with an assumption of the linearization of the bulk and inversion charges with respect to the surface potential at a fixed gate bias, the BSIM5 model is directly derived from the solution of the Poisson equation coupled to the current density equation. The comparisons of the inversion charge and the channel current between the BSIM5 and the Pao–Sah model indicate that the BSIM5 model maintains the inherent device physics and high accuracy of the Pao–Sah model. BSIM5 model is further extended to include the short-channel effects, narrow-width-effects, and the wide comparison with the experiment data demonstrates its validity to simulate the nanoscale circuits. Moreover, the symmetry and RF function of BSIM5 have also been demonstrated in the Gummel tests and high-order distortion analysis.

Optimal cascade lumped model of deep submicron on-chip interconnect with distributed parameters

A rapidly responding yet highly accurate on-chip interconnect simulation model, an optimal cascade lumped model, is presented. Compared with previous interconnect simulating models with similar parameters, the new model expends less CPU time and provides simple closed-form expressions for accurate number of repeated RLCG or LC models, which are proved by the simulation results of 0.18, 0.13, 0.07 and 0.05 μm. It is valuable to guide the analysis and the simulation of deep submicron VLSI circuits with billions of interconnects.

Multigranular Parallel Algorithms for Solving Linear Equations in VLSI Circuit Simulation

Algorithms for parallel execution of forward elimination to solve linear equations arising from very large scale integrated circuit simulation are discussed. Here, a multigranular method is introduced, exploiting different levels of potential parallelism. According to these levels, the new method contains four phases, which are dynamically linked. Therefore, the use of an architecture with shared memory in connection with multithreaded programming enables the parallelization of a serial well-adapted sparse-matrix solver. In order to take system-specific properties into account, an adaptive partitioning is proposed. For this, the partition size is enlarged step by step as long as the measured execution time decreases. Applying this method to industrial examples an efficiency of processor usage of nearly 90%, with up to 12 processors, is reached for relevant circuits.

Metamorphic programming: unconventional high performance

A programming methodology that violates most of the rules of good programming has shown spectacular reductions in simulation times on several benchmarks. Applying this technique in logic-level VLSI circuit simulation also improved simulation performance. For a new VLSI circuit, faster simulation translates into faster time to market, so even the most peculiar programming type is worth exploring if the carrot is increased performance. Discovering efficient and effective metamorphic programming techniques across a range of problems outside simulation will require a concerted effort across the software community. The most important problem is the lack of metamorphic constructs in mainstream high-level languages.

A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits

A multilayered integrated circuit (IC) package structure is composed of many signal layers, power layers, and ground layers. Particularly, the whole planes are assigned for the power and ground of the system. Accordingly, the generic circuit representation of such a complicated multilayer IC package becomes too complicated to efficiently evaluate its electrical performance. In this work, a novel compact package circuit model for the efficient simulation and analysis of such complicated IC packages is presented. Unlike the conventional models, current distributions within the package are modeled by introducing a compact partial plane circuit model. Thus, the proposed package model is much simpler than the conventional generic circuit models, while its accuracy is preserved. Thereby, today's complicated IC packages can be efficiently evaluated and analyzed. Its accuracy and efficiency are verified by benchmarking it with a conventional generic package circuit model; this conventional model may not be practical to use for package evaluation and analysis. It is then shown that the proposed model can be efficiently applied for the signal integrity verification of complicated IC packages and high-performance VLSI circuits.

Realistic and efficient simulation of electro-thermal effects in VLSI circuits

Needs for electro-thermal simulation of VLSI circuits, as opposed to both the system and device levels, are analyzed. A system capable of modeling these effects in a realistic and sufficiently accurate way that uses a reasonable amount of CPU resources is presented. An innovative solver is also proposed. The system is used to study the importance of some three dimensional (3-D) effects as well as metallic connections. A complete example was treated to have an insight on the type of results to be expected and the corresponding costs in terms of CPU.

A modified noising algorithm for the graph partitioning problem

Many heuristics such as iterative improvement and simulated annealing are available in the literature which try to give a near-optimal solution to the graph partitioning problem. Recently, a new method called the noising method has been proposed for solving combinatorial optimization problems. The noising method has been successfully employed to solve the clique partitioning problem. We extend the method to solve the graph partitioning problem. We also propose a modified noising method (algorithm) for efficient solution of the graph partitioning problem. We evaluate the performance of our algorithm for solving both the problems, viz., the clique partitioning problem using random graphs and the graph partitioning problem using concurrent VLSI circuit simulation program graphs. We compare our algorithm with the original noising and the simulated annealing algorithms. The results show that our modified noising algorithm compares favourably with the original noising and the simulated annealing algorithms, both in terms of the run time and the quality of the solutions obtained.

A new approach for partitioning VLSI circuits on transistor level

For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects between the subcircuits and balanced subcircuit sizes is presented. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.

Digital VLSI circuit design and simulation of an adaptive resonance theory neural network

A digital VLSI circuit design for an adaptive resonance theory (ART) neural network architecture, called the augmented ART-1 neural network (AARTI-NN) is presented. An ‘axon-synapse-tree’ structure is used to realize the activities of the short-term memories and reset subsystem. The long-term memory traces are implemented using NMOS transmission gales. PSpice circuit simulation was carried out to verify the design of a prototype, seven-node AARTI-NN. A clock-controlled delay element is included in the simulation to illustrate the functionality of the AARTI-NN. It is shown that the AARTI-NN node selection activities simulated from the circuit designed are identical to those described by the coupled differential equations governing the AARTI-NN.

Robust VLSI circuit simulation techniques based on overlapped waveform relaxation

High-performance mainframe computers are commonly implemented using bipolar VLSI technologies. The simulation of such circuits is very time-consuming using traditional direct methods, as in SPICE. Relaxation-based methods such as waveform relaxation (WR) have been used to speed up the simulation of MOS circuits, but they have not been as effective for bipolar circuits because of the strong coupling between logic gates. In this paper, a fast, robust overlapped waveform relaxation (OWR) algorithm is presented. OWR is effective for bipolar circuits because it uses an overlapped partitioning strategy to overcome the effect of strong coupling on convergence speed. To demonstrate the effectiveness of this algorithm, simulation results are presented for combinational and sequential digital bipolar circuits as well as analog bipolar circuits. From the simulation results, it can be concluded that the speed advantage of OWR compared to the direct method increases with circuit size. The OWR algorithm is more robust than standard WR; it converges in cases where WR diverges or converges too slowly. OWR is about two times faster than WR for tightly coupled bipolar circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A ferroelectric capacitor macromodel and parameterization algorithm for SPICE simulation

A compact equivalent circuit model, or macromodel, is presented which reproduces both the DC charge storage and transient switching current responses of a ferroelectric capacitor. The macromodel circuit element values are rigorously linked to physical quantities which are readily characterized with simple electrical measurements. A software package is described which both parameterizes and optimizes the model to measured data and outputs a SPICE input file. Together, the macromodel and parameterization software form a complete linkage between material characterization and circuit design which is largely transparent to the design engineer. Optimization results lend insight into the underlying theory of ferroelectric switching and the sources of nonideal charge storage. SPICE simulations demonstrate the utility of the macromodel for VLSI circuit simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A direct method for BBD matrix inversion

In VLSI circuit simulation, large systems of equations are solved. In order to do that the system is partitioned into groups of tightly coupled variables, called blocks, such as the subcircuits in the VLSI structure. Further, the equations are ordered by subcircuits to produce a matrix in a bordered block diagonal form. Each diagonal block represents the internal variables of a subcircuit, and the border represents the interconnections among the subcircuits.

BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits

The BSIM plus MOS transistor model is developed for simulation of digital and analog VLSI circuits in advanced submicron technologies. A compact parameter set is carefully selected to accurately characterize transistors and achieve continuity of the drain current and its derivatives across the different regions of operation. Several submicron modeling techniques are described. Simulated results agree well with measured data of transistors from two industrial technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Corolla partitioning for distributed logic simulation of VLSI-circuits

Time Warp has evolved to a common technique for distributed simulation. Speedup in Time Warp simulation systems mainly depends on two overhead factors: first, the load on the simulators has to be well balanced and second, communication and rollbacks have to be kept to a minimum. Both of these factors are influenced by the partitioning of the simulated system. In this paper, we focus on various static partitioning schemes used to partition digital circuits for distributed simulation. A new hierarchical partitioning approach is presented, compared and rated with other partitioning schemes by evaluating benchmark circuits. Partitioning is done in two steps: a fine grained clustering step based on corollas and a coarse grained step forming partitions using the connectivity matrix. The corolla approach yields very good partitioning results even for a large number of partitions. The achieved speedups are almost linear (up to 12 partitions for larger circuits), as long as the partition sizes are large enough so that communication between the simulators is not a bottleneck. The results reveal the great impact of partitioning on the acceleration of distributed logic simulation and show the effectiveness of the presented corolla partitioning scheme.

OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms

A device model parameter optimization program, OPTIMA, for extracting parameter values of empirical and/or analytical models most commonly used for VLSI circuit simulation, is described. Such device models often have parameters which are correlated, and some of them could be redundant. OPTIMA can automatically detect redundant model parameter combinations. This not only allows one to extract more meaningful parameters, but also helps in the development of improved physical models with a minimum number of empirical parameters. The parameter redundancy is detected using a statistical confidence region algorithm which can be implemented as a postprocessor to any gradient-based least-squares optimization method. The advantage of the statistical confidence region algorithm in OPTIMA, as applied to MOSFET model parameter extraction, is discussed, using examples from drain and substrate current modeling. >

Efficient VLSI fault simulation

Let C be an acyclic Boolean circuit with n gates and ≤ n inputs. A circuit manufacture error may result in a “Stuck-at” (S-A) fault in a circuit identical to C except a gate v only outputs a fixed Boolean value. The S-A fault simulation problem for C is to determine all possible (S-A) faults which can be detected (i.e., faults circuit and C would give distinct outputs) by a given test pattern input. We consider the case where C is a tree (i.e., has fan-out 1.) We give a practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C. Our algorithm required only the evaluation of a circuit FS( C) which has ≤ 7 n gates and has depth ≤ 3( d + 1), when d is the depth of C. Thus the sequential time of our algorithm is ≤ 7 n, and the parallel time is ≤ 3( d + 1). Furthermore, FS( C) requires only a small constant factor more VLSI area than does the original circuit C. We also extend our results to get efficient methods for fault simulation of oblivious VLSI circuits with feedback lines.

Massive parallelism in multi-level simulation of VLSI circuits

The growing complexity of VLSI systems leads to the need of developing new generation CAD tools that allow us to produce results in a short time. In particular, simulation is a key task where the time response represents a critical point for the interaction between the designer and the tool. Simulation time can be reduced both by developing new fast algorithm and by using dedicated architectures to exploit simulation features. Dedicated architectures that support circuit simulation usually have very high implementation costs and are hardly scalable to workstation prices. The necessity to resort to high-end solutions is due to the event-driven paradigm that minimizes the number of evaluations, but also limits the exploitable parallelism, and requires dynamic management of communications and dynamic load balancing. As an alternative, we propose a massively parallel approach to support VHDL multi-level simulation of circuits that relies on an extension of the compiled model and shows interesting results in terms of simulation acceleration and cost effectiveness. Features of the architecture include: a virtually unlimited speed-up constrained only by the number of processing units and communication paths; implementation scalability without algorithmic modifications; low cost of the single processing unit, that can be based on a RISC-like processor and implemented with Wafer Scale Integration techniques; high performance in terms of simulation time. For instance, an architecture with 256 processors and 16 2-bit communication buses performs in the range of billions of gate evaluations per second, thus showing competitiveness with the best event-driven machine.