Robust VLSI circuit simulation techniques based on overlapped waveform relaxation

Abstract

High-performance mainframe computers are commonly implemented using bipolar VLSI technologies. The simulation of such circuits is very time-consuming using traditional direct methods, as in SPICE. Relaxation-based methods such as waveform relaxation (WR) have been used to speed up the simulation of MOS circuits, but they have not been as effective for bipolar circuits because of the strong coupling between logic gates. In this paper, a fast, robust overlapped waveform relaxation (OWR) algorithm is presented. OWR is effective for bipolar circuits because it uses an overlapped partitioning strategy to overcome the effect of strong coupling on convergence speed. To demonstrate the effectiveness of this algorithm, simulation results are presented for combinational and sequential digital bipolar circuits as well as analog bipolar circuits. From the simulation results, it can be concluded that the speed advantage of OWR compared to the direct method increases with circuit size. The OWR algorithm is more robust than standard WR; it converges in cases where WR diverges or converges too slowly. OWR is about two times faster than WR for tightly coupled bipolar circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>