Silvaco Technology Computer-aided Design Research Articles

A Method to Simulate Extrinsic Light Excitation of Vanadium-Compensated 6H-SiC

Extrinsic light excitation has much lower absorption coefficient compared to intrinsic light excitation, which can better utilize the “bulk” of semiconductor rather than a thin surface as the depth of light absorption is much larger, making it suitable for higher power applications. However, commercial technology computer aided design (TCAD) software has not developed a model for extrinsic light excitation. Therefore, we construct a model of Vanadium-compensated semi-insulating (VCSI) 6H-SiC photoconductive semiconductor switch (PCSS) illuminated with sub-bandgap light, and realize the process of light absorption at V deep acceptor level in Silvaco TCAD simulation by modifying the electron emission rate. Then, we simulate the transient response of 6H-SiC triggered by a nanosecond light pulse and discuss the feasibility of this method.

Modeling and Simulation of Fe-Doped GaN PCSS in High-Power Microwave

In this article, the characteristics of linear GaN photoconductive semiconductor switch (PCSS) in high-power microwaves are investigated by Silvaco TCAD (Technology Computer-Aided Design). By comparison of optical absorption efficiency among three types of PCSS structures, the optimized Fe-doped GaN PCSS is designed in a side-illuminated, vertical structure with a spot size of 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 8 mm. The photocurrent of side-illuminated GaN vertical PCSS (vPCSS) begins to saturate at 1.65 mJ with the increase of applied optical energy. The average saturated switch resistance and electron concentration of vPCSS under a bias voltage of 5–20 kV are almost 8.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pmb\Omega $</tex-math> </inline-formula> and 3.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{14}}$</tex-math> </inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-\text{3}}$</tex-math> </inline-formula> , respectively. As the device is in a saturated photocurrent state, the peak photocurrent is a linear function of bias voltage. As the device is in an unsaturated photocurrent state, improving the light energy is more effective than the withstand voltage of the device to increase photocurrent. Due to the short carrier lifetime, the GaN vPCSS has the response capacity to a 50-ps pulsewidth laser. Based on side-illuminated GaN vPCSS at the bias field 200 kV/cm, a narrowband microwave with adjustable frequency (3.3–5 GHz) could be generated. The maximum output power reaches up to 1.3 kW. Effects of anti-reflective (AR) and reflective coatings on optical absorption are investigated. The photocurrent of vPCSS with both AR and reflective coatings increases by 77.2% as compared with normal vPCSS.

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10&lt;sup&gt;-17&lt;/sup&gt; farads and 1.11x10&lt;sup&gt;-12&lt;/sup&gt; seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

In this study, the degradation of the subthreshold swing (S.S.) and the hump effect are observed in the local oxidation of silicon (LOCOS) metal-oxide-semiconductor field-effect transistors (MOSFETs) under short-and long-term positive bias temperature instability tests, respectively. S.S. collapse is considered to be caused by anode hot-hole injection, and the hump effect occurs because the geometric structure from LOCOS isolation forms parasitic transistors on both sides of the channel, which can be verified by a Silvaco Technology computer-aided design (TCAD) simulation. In addition, the body effect measurement method is proposed to elucidate the mechanism of the hump effect for further confirmation of hump formation.

Normally-OFF AlGaN/GaN-based HEMTs with decreasingly graded AlGaN cap layer

In this work, an enhancement-mode (E-mode) AlGaN/GaN-based high-electron-mobility transistor (HEMT) with a graded AlGaN cap layer (GACL) is proposed and numerically studied by Silvaco technology computer-aided design. The GACL is designed with a decreasingly graded Al composition x along [0001] direction and the initial x is smaller than the Al composition of the Al0.2Ga0.8N barrier layer (BL). This GACL scheme can simultaneously produce high-concentration polarization-induced holes and negative net polarization charges at the GACL/BL interface. This can facilitate the separation of the conduction band (E C) and Fermi level (E F) at the 2DEG channel and therefore benefit the normally-OFF operation of the device. The optimized graded-AlGaN-gated metal-semiconductor HEMT can achieve a large threshold voltage of 4 V. Furthermore, we demonstrated that shortening the gate length on the GACL and inserting an oxide layer between the gate and GACL can be both effective to suppress gate leakage current, enhance gate voltage swing, and improve on-state drain current of the device. These numerical investigations can provide insights into the physical mechanisms and structural innovations of the E-mode GaN-based HEMTs in the future.

Understanding Performance Limitation of CuCdSnS as Photoactive Layer: Physics of Defect States and Recombination Mechanisms

There is a plethora of thin-film photovoltaic materials like copper indium gallium sulfur (CIGS), CIGS-Selenium (CIGSSe), Cu2ZnSnS4 (CZTS), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {Cu}_{{2}}\text {ZnSn} (\text {S}_{x}, \text {Se}_{{1}-{x}})_{{4}}$ </tex-math></inline-formula> (CZTSSe), and so on that are currently under research and are suitable for commercial use. In this study, a Cu2CdSnS4 (CCdTS)-based thin-film solar cell is simulated using Silvaco technology computer-aided design (TCAD) to extract its optical and electrical properties such as efficiency, electric field (EF), short circuit current, quantum efficiency, and so on. The device is also optimized by variations in physical parameters such as thickness, doping concentration, and material defects of the absorber layer. A remarkable efficiency of 21.2% is reached under the condition of defect absence, whereas the efficiency of 7.5% is obtained for the defect present in the absorber layer. Changes in the behavior of the solar cell with material defects following Gaussian- and tail-type distribution are also analyzed and corresponding conclusions are drawn.

Design and analysis of a double gate SiGe/Si tunnel FET with unique inner-gate engineering

An inner-gate engineered double gate heterostructure tunnel field effect transistor (SiGe/Si-IGTFET) has been presented. The inner-gate is grown at the center of the Si0.6Ge0.4/Si TFET, followed by a thin HfO2 dielectric layer. The drain current performance of the suggested device has been investigated comprehensively to discover its efficacy. The device provides much-lower ambipolarity (by 6 decades) compared to heterostructure TFET with a similar dimension. The SiGe/Si-IGTFET device has also shown higher immunity against short channel effects such as drain induced barrier lowering and gate induced drain leakage current (I GIDL). To examine the impact of inner-gate, various DC parameters such as ambipolar current (I amb), on current (I on), I on/I amb current ratio, average subthreshold swing (SS), surface potential, and electric field have been considered. The device offers a much improved current ratio (I on/I amb) of 1.78 × 1012 with an average SS of 23 mV decade−1 by optimizing the position and dielectric material of the inner-gate. The simulation of the suggested device is carried out using a 2D Silvaco Technology Computer-Aided Design (TCAD) device simulator.

Design of vertical diamond Schottky barrier diode with junction terminal extension structure by using the n-Ga2O3/p-diamond heterojunction

A novel junction terminal extension structure is proposed for vertical diamond Schottky barrier diodes (SBDs) by using an n-Ga2O3/p-diamond heterojunction. The depletion region of the heterojunction suppresses part of the forward current conduction path, which slightly increases the on-resistance. On the other hand, the reverse breakdown voltage is enhanced obviously because of attenuated electric field crowding. By optimizing the doping concentration, length, and depth of n-Ga2O3, the trade-off between on-resistance and breakdown voltage with a high Baliga figure of merit (FOM) value is realized through Silvaco technology computer-aided design simulation. In addition, the effect of the work functions of the Schottky electrodes is evaluated. The results are beneficial to realizing a high-performance vertical diamond SBD.

Investigation on Capacitance Collapse Induced by Secondary Capture of Acceptor Traps in AlGaN/GaN Lateral Schottky Barrier Diode.

In this study, a dedicated dynamic measurement system was used to investigate the transient capacitance and recovery process of AlGaN/GaN lateral Schottky barrier diodes (SBDs). With the consideration of acceptor traps in the C-doped buffer, the C-V characteristics and transient capacitance were measured and analyzed, and the results were simulated and explained by Silvaco TCAD (technology computer aided design). The ionization of acceptor traps and the change of electric potential were monitored in transient simulation to investigate the origin of the capacitance collapse in the SBD. The results suggest the significant impact of traps in the GaN buffer layer on the capacitance collapse of the device, and the secondary capture effect on the variation of acceptor ionization. Based on the study of transient capacitance of SBD, this work could be extended to the Miller capacitance in high electron mobility transistor (HEMT) devices. Moreover, the report on the stability of capacitance is essential for GaN devices, and could be further extended to other aspects of device research.

RF/Analog and Linearity Performance Evaluation of Lattice-matched Ultra-thin AlGaN/GaN Gate Recessed MOSHEMT with Silicon Substrate

In this article, the authors have demonstrated and analyzed various analog/RF, and linearity performances of an AlGaN/GaN gate recessed MOSHEMT (GR-MOSHEMT) grown on a Si substrate with mathematical modeling based Technology Computer-Aided Design (TCAD) simulation. Specifically, an Al2O3 dielectric GR-MOSHEMT has shown tremendous potential in terms of AC/DC figure of merits (FOM’s) such as low leakage current, high transconductance, high Ion/Ioff current ratio, and excellent linear properties corresponding to conventional AlGaN/GaN HEMT and MOSHEMT. The figure-of-merit metrics such as VIP2, VIP3, IIP3, and IDM3 are performed for the different drain to source voltages (VDS) of 2.5 V, 5 V, and 10 V. All the modeling and simulation results are generated by Commercial Silvaco TCAD and found to be satisfactory in terms of high frequency and power applications. The present GR-MOSHEMT device shows superior performance with a threshold voltage of 0.5 V, a Current density of 888 mA, a high transconductance of 225 mS/mm, and a high unit gain cut-off frequency 0.91GHz. The developed AlGaN/GaN GR-MOSHEMT considerably improves the device performance and is also suitable for high power distortion-less RF applications.

Reducing the Source Resistance by Increasing the Gate Effect on Substrate for Future Terahertz HEMT Device

In this paper, we present the dependence of source resistance sensibility on the gate bias effect in a High Electron Mobility Transistor (HEMT) using the Drift-Diffus (D-D) model with the SILVACO Technology Computer-Aided Design (TCAD) tool. The obtained results show that the increases of gate bias effect on substrate lead to decreasing the source resistance of the simulated device. The reported increase in the effect of gate induces the increases of transferred holes concentration towards the source region and which induce the decreases of source resistance. The decrease of source resistance can also be made by reducing the buffer thickness which leads to an increase in the gate effect on the substrate. The source resistance value is influenced by the Drain-Induced Barrier Lowering (DIBL) effect where the rate of decreasing the source resistance will be decreasing consequently to increase the drain bias. The reduction of the source resistance induces the increase of device sensibility for lows values of current.

Investigation on Dynamic Characteristics of AlGaN/GaN Lateral Schottky Barrier Diode.

This work investigates the transient characteristics of an AlGaN/GaN lateral Schottky barrier diode (SBD) and its recovery process with a dedicated dynamic measurement system. Both static and dynamic characteristics were measured, analyzed with the consideration of acceptor/donor traps in the C-doped buffer and GaN channel, and verified by Silvaco TCAD (technology computer aided design) simulations. The energy band, electric field, and electron concentration were monitored in the transient simulation to study the origin of the current collapse in the SBD. Using the verified model, the impact of carbon doping concentration in the buffer and the thickness of the unintentionally doped (UID) GaN channel in the transient behavior was estimated. Several observations were revealed. Firstly, the traps in the GaN channel and buffer layer have a significant impact on the current collapse of the device. A severe deterioration of current collapse can be observed in the SBDs with increasing density of acceptor-like traps. Secondly, the current collapse increases with the thinner UID GaN channel layer. This well-performed simulation model shows promise to be utilized for the dynamic performance optimization of GaN lateral devices.

Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

Modeling and simulation of bifacial perovskite/PERT-silicon tandem solar cells

In this paper, we physically modeled a bifacial perovskite/PERT-silicon tandem solar cells for the first time using Silvaco technology computer-aided design simulator (TCAD). The cell model was calibrated with the reported experimental data of perovskite solar cell (PSC) and PERT-silicon solar cell. The effects of perovskite thickness (tpvk) and perovskite bandgap were investigated on the performance of bifacial tandem solar cells under different albedo. The simulation results predict that the optimum tpvk increases with albedo intensities because a thicker perovskite layer is needed to facilitate current matching for high albedos. Moreover, the tpvk tolerance for a high-efficiency bifacial tandem solar cell increases with albedo. The simulation results reveal an efficiency over 31.9% for 0.45–1 μm of tpvk with 1.65–1.75 eV perovskite bandgap for a bifacial tandem cell under 30% albedo. Additionally, compared to the monofacial cell, the tandem design shows an enhancement of about 30% at the spectral albedo level of common grounds like concrete. The simulation and analysis presented in this work can help optimize perovskite/silicon tandem cell manufacturing to achieve higher power conversion efficiencies.

Investigating Heavy-Ion Effects on 14-nm Process FinFETs: Displacement Damage Versus Total Ionizing Dose

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no “rebound” in the ON-state current back to its initial high value; however, the OFF-state current “rebound” was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects.

Design and Implementation of a pH Sensor for Micro Solution Based on Nanostructured Ion-Sensitive Field-Effect Transistor.

pH sensors based on a nanostructured ion-sensitive field-effect transistor have characteristics such as fast response, high sensitivity and miniaturization, and they have been widely used in biomedicine, food detection and disease monitoring. However, their performance is affected by many factors, such as gate dielectric material, channel material and channel thickness. In order to obtain a pH sensor with high sensitivity and fast response, it is necessary to determine the appropriate equipment parameters, which have high processing cost and long production time. In this study, a nanostructured ion-sensitive field-effect transistor was developed based on the SILVACO technology computer-aided design (TCAD) simulator. Through experiments, we analyzed the effects of the gate dielectric material, channel material and channel thickness on the electrical characteristics of the nanostructured field-effect transistor. Based on simulation results, silicon nitride was selected as the gate dielectric layer, while indium oxide was chosen as the channel layer. The structure and parameters of the dual channel ion-sensitive field-effect transistor were determined and discussed in detail. Finally, according to the simulation results, a pH sensor based on the nanostructured ion-sensitive field-effect transistor was fabricated. The accuracy of simulation results was verified by measuring the output, transfer and pH characteristics of the device. The fabricated pH sensor had a subthreshold swing as low as 143.19 mV/dec and obtained an actual sensitivity of 88.125 mV/pH. In addition, we also tested the oxidation reaction of hydrogen peroxide catalyzed by horseradish peroxidase, and the sensitivity was up to 144.26 pA mol−1 L−1, verifying that the ion-sensitive field-effect transistor (ISFET) can be used to detect the pH of micro solution, and then combine the enzyme-linked assay to detect the concentration of protein, DNA, biochemical substances, biomarkers, etc.

Device simulations of a novel nanostructured CdS/CdTe solar cell with back contacts

Device simulations of a novel nanopillar-based n-CdS/p-CdTe solar cell with back contacts are carried out using the SILVACO technology computer-aided design (TCAD) device simulator. The device consists of nanopillars of CdTe coated with a very thin layer of CdS. It is shown that, for nanopillars with increasing height but given width as well as increasing width and given height, device performance parameters such as the open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor, and solar cell conversion efficiency (η) increase. However, there is an optimum number of nanopillars that can be integrated into a given device area, while integration of more or fewer than this optimum value will deteriorate the device performance.

Modeling and simulation of a dual-material asymmetric heterodielectric-gate TFET

Analytical modeling of a dual-material asymmetric heterodielectric-gate tunnel field-effect transistor (FET) is carried out based on the Poisson equation and parabolic approximation techniques. An asymmetric gate with two materials having different work functions is used to eliminate the influence of the OFF-current (leakage current) and short-channel effects in the device. The lengths of metal 1 and metal 2 are taken to be 10 nm and 10 nm, respectively, and the device performance is analyzed. Expressions for the surface potential, electric field, and drain current are obtained by using a two-dimensional (2D) mathematical model, whose results are compared with those obtained using the Silvaco technology computer-aided design (TCAD) simulator, revealing good agreement. The proposed dual-material asymmetric gate tunnel FET produces an improved ON-current of 10−5 A/µm and a decreased OFF current of 10−10 A/µm, with an ON/OFF ratio of 105.

Simulation design of a high-breakdown-voltage p-GaN-gate GaN HEMT with a hybrid AlGaN buffer layer for power electronics applications

We propose a novel GaN high-breakdown-voltage high-electron-mobility transistor (HB-HEMT) with a p-GaN gate and hybrid AlGaN buffer to improve the breakdown voltage and Baliga’s figure of merit. The hybrid AlGaN buffer is composed of a horizontally arranged AlaGa1−aN zone and an AlbGa1−bN zone, each having different Al compositions a and b. The proposed HB-HEMT is simulated using the Silvaco technology computer-aided design (TCAD) tool ATLAS, considering the polarization model, low-field mobility, high-field mobility, and Selberherr’s impact ionization model to simulate the direct-current (DC), breakdown, and C–V properties of the proposed HB-HEMT. The breakdown voltage of the HB-HEMT is significantly improved by introducing the hybrid AlGaN buffer structure, which can effectively modulate the electric field distributions within the channel and the buffer. A high breakdown voltage (1450 V), a low specific on-state resistance (0.47 mΩ cm2), and a high Baliga’s figure of merit (4.47 GW/cm2) are obtained at the same time with an Lgd (gate-to-drain distance) of 6 µm, a distance from the gate to the AlaGa1−aN/AlbGa1−bN interface of 4 µm, and Al compositions of a = 0.25 and b = 0.1. The simulated C–V results also reveal that the GaN HB-HEMT shows better switching characteristics than the conventional GaN HEMT with a p-GaN gate.

Improving a-InGaZnO TFTs Reliability by Optimizing Electrode Capping Structure Under Negative Bias Illumination Stress

This study enhances the reliability of via-contact type amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with optimal contact capping area under negative bias illumination stress (NBIS). The $\text{I}_{\text {D}}$ - $\text{V}_{\text {G}}$ transfer curves for source and drain electrodes with no capping area exhibited a larger negative threshold voltage ( $\text{V}_{\text {TH}}$ ) shift after NBIS. Similarly, the drain electrode with capping area also shows serious electrical degradation. Compared to these two electrode types, however, a source electrode with capping area exhibited excellent stability after NBIS due to the lack of holes injecting into the gate oxide near source side. This optimal contact capping area provides a novel device structure which improves NBIS reliability. Finally, this work utilizes the SILVACO technology computer-aided design (TCAD) simulation to demonstrate the changes in the energy band and electron field distribution after NBIS for different capping metal structures. Then the hole injection and electrical degradation mechanisms are verified.