Silvaco TCAD Simulation Research Articles

Breakdown characteristics of deep-ultraviolet Al0.6Ga0.4N p-i-n avalanche photodiodes

A top-illuminated deep-ultraviolet Al0.6Ga0.4N p-i-n avalanche photodiode (APD) structure was designed and grown by metalorganic chemical vapor deposition on an AlN bulk substrate and on two different quality AlN/sapphire templates, and APDs were fabricated and tested. The APD devices with a circular diameter of 20 μm have demonstrated a distinctive reverse-bias breakdown behavior. The reverse breakdown voltage of the APDs is approximately −140 V, which corresponds to a breakdown electric field of 6–6.2 MV/cm for the Al0.6Ga0.4N material as estimated by Silvaco TCAD simulation. The APDs grown on the AlN bulk substrate show the lowest leakage current density of <1 × 10−8 A/cm2 (at low reverse bias) compared to that of the devices grown on the AlN templates. From the photocurrent measurement, a maximum gain (current limited) of 1.2 × 104 is calculated. The average temperature coefficients of the breakdown voltage are negative for APD devices fabricated from both the AlN bulk substrate and the AlN templates, but these data show that the coefficient is the least negative for the APD devices grown on the low-dislocation-density AlN bulk substrate.

I–V Characteristics of E-mode GaN-based transistors under gate floating

This study investigates the I–V behaviors of various E-mode GaN-based transistors under gate floating and zero gate bias. The p-GaN gate high electron mobility transistor (HEMTs), gate injection transistors, and Cascode GaN FETs have been adopted and compared. The high off-state drain current is observed under gate floating except for Cascode GaN FETs based on the measured I–V characteristics. The off-state drain current of p-GaN gate HEMT is up to 0.8 mA under gate floating at a drain bias of 6 V, which is about 107 times larger than zero gate bias. The devices will induce false-turn-on and reverse conduction loss during switching under gate floating due to the capacitance charging effect between the drain and the gate electrodes. The mechanism of the capacitance charging effect is discussed using the equivalent circuit of p-GaN gate HEMTs and confirmed by Silvaco TCAD simulation.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p+ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p+ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance (R on,sp). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage (V BR) and R on,sp () of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.

Influence of sub-bandgap illumination on electric field distribution at grain boundary in CdZnTe crystals

<sec>Grain boundary is one of the main defects, limiting the large-area application of CdZnTe nuclear radiation imaging detectors. In order to explore the ways to improve the electric field distribution properties near grain boundary, the effect of sub-bandgap illumination on the electric field distribution in CdZnTe detector with grain boundary is studied by Silvaco TCAD simulation technique. The grain boundary potential barrier and electric field dead zone are found in simulation results that significantly affect the carrier transport process in CdZnTe detector. The electric field dead zone caused by the grain boundary disappears under the bias of sub-bandgap illumination. Thus the electric field distribution tends to be linear. Meanwhile, the effects of different wavelengths and intensities of sub-bandgap illumination on the electric field distribution at the grain boundary are also investigated. The results show that the electric field of CdZnTe is distorted by sub-bandgap illumination at an intensity lower than 1×10<sup>–9</sup> W/cm<sup>2</sup>. In contrast, a flatter electric field distribution is achieved at a wavelength of 850 nm and an intensity of 1×10<sup>–7</sup> W/cm<sup>2</sup>. The carriers can be transported by drifting, reducing the probability of being captured or recombined by defects during transport, thus improving the charge collection efficiency of the detector.</sec><sec>In addition, the microscopic mechanism of the modulation of the electric field distribution by sub-bandgap illumination and the energy band model of CdZnTe crystal containing grain boundary are proposed. Owing to the existence of the grain boundary, two space charge regions are formed near the grain boundary. The energy band at the grain boundary is bent upward. Meanwhile, the metal-semiconductor contact forms a Schottky barrier, and the energy band near the electrode is bent upward. When the bias voltage is applied, the energy band structure of the CdZnTe tends to tilt from the cathode to the anode. The sub-bandgap illumination can lower the energy band barrier at the grain boundary and regulate the energy band on both sides of the grain boundary. It is believed that this discussion will also make some contributions to understanding of the effects of illumination and grain boundary in other types of optoelectronic devices, especially the applications of thin films in solar cells and detectors.</sec>

A modified pseudo 2D physically-based model for double-gate TFETs: Role of precise calculations of drain and source depletion regions

In this current study, a modified pseudo two-dimensional (2-D) semi-analytical model for double gate tunnel FETs (DG-TFETs) is introduced. The main regions in the DG-TFET structure are the channel and the depletion regions inside the source and the drain. In such regions, the 2-D Poisson's equation is solved by adjusting suitable boundary conditions. The source and the drain depletion region lengths are calculated precisely by an iterative technique resulting in an accurate prediction of the electrostatic potential. According to the obtained 2-D electrostatic potential, the energy band diagram could be extracted and, consequently, the minimum tunneling width is calculated. Accordingly, the model of drain current is introduced by applying Kane's tunneling model. Further, the source depletion charge and the channel charge are derived, and the terminal capacitance components are then extracted. A comparison between the proposed model and SILVACO TCAD simulations shows a satisfactory agreement that confirms the validation of the presented model robustness.

Optimization techniques for p-GTO thyristor design

A new type of semiconductor power device was devised in the early ’90s as an alternative to the classic Gate Turn-Off (GTO) thyristor. Because the low-doped n-base was replaced by a low-doped p-base, it was called the p-GTO. Its main advantage is a higher possible control voltage when the device is switched off, leading to the possibility of a higher blocking anode current (IATO) and a lower turn-off time. The studies and techniques employed with the help of SILVACO-TCAD simulation software Athena and Atlas show that the p-GTO has higher breakdown voltages compared with its classic counterpart and similar on-state voltage (VT) and switching characteristics when replacing the GTO in the same circuit. Specific circuit improvements, like an affordable higher turn-off gate voltage, will drive the p-GTO into even faster switching operation.

Prediction and Simulation of electrical and optical characteristics of an OLED based on P3BEdotBT3A organic material

The OLED “organic light-emitting diode” has been highly industrialized for several years, especially since their use in smartphones and televisions. OLEDs have attracted a lot of attention because of their desirable characteristics including their low consumption of electrical energy, their flexibility... Our work focuses on the simulation of a single-layer OLED based on an organic material (ITO/P3BEdotBT3A/Ca) using the SILVACO-TCAD simulation software. This simulation allowed us to visualize the operational distribution of Langevin recombination within the proposed structure, and to determine the electrical and optical characteristics, such as luminescence power, current versus electric field, and current versus voltage (the I-V characteristics) for different thicknesses and doping concentration of the emitting layer.

Boosting on Current Using Various Source Material for Dual Gate Tunnel Field Effect Transistor

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

Performance Analysis of TFET and VDSTFET for Low Power Application using the Work Function Engineering

We report a design of TFET which is quite different from conventional TFET. The structure of VTFET is similar to MOSFET but the conducting mechanism is completely different. Vertical TFET is designed perpendicular to the horizontal plane. The switching and carrier transportation mechanism of VTFET is based on the mechanism of the band to band tunneling through a potential barrier and vertical TFET is based on tunneling perpendicular to the device rather than a mechanism like thermionic emission unlike in MOSFET. We have designed a model for the two-dimension structure of V-TFET which consists of the dual-source and single drain. The channel among the drain and gate region is extraordinarily thin. We have plotted the transfer characteristics of V-TFET according to device parameters using TCAD. The comparison of VTFET with DSVTFET is done by using Silvaco TCAD and the effect of source doping, and work function on transfer characteristics of the device is examined by using silvaco TCAD simulations. The proposed device produces a low-off current.

High-Sensitivity pH Sensor Based on Coplanar Gate AlGaN/GaN Metal-Oxide-Semiconductor High Electron Mobility Transistor

The sensitivity of conventional ion-sensitive field-effect transistors is limited to the Nernst limit (59.14 mV/pH). In this study, we developed a pH sensor platform based on a coplanar gate AlGaN/GaN metal-oxide-semiconductor (MOS) high electron mobility transistor (HEMT) using the resistive coupling effect to overcome the Nernst limit. For resistive coupling, a coplanar gate comprising a control gate (CG) and a sensing gate (SG) was designed. We investigated the amplification of the pH sensitivity with the change in the magnitude of a resistance connected in series to each CG and SG via Silvaco TCAD simulations. In addition, a disposable extended gate was applied as a cost-effective sensor platform that helped prevent damages due to direct exposure of the AlGaN/GaN MOS HEMT to chemical solutions. The pH sensor based on the coplanar gate AlGaN/GaN MOS HEMT exhibited a pH sensitivity considerably higher than the Nernst limit, dependent on the ratio of the series resistance connected to the CG and SG, as well as excellent reliability and stability with non-ideal behavior. The pH sensor developed in this study is expected to be readily integrated with wide transmission bandwidth, high temperature, and high-power electronics as a highly sensitive biosensor platform.

Double-Barrier β-Ga2O3 Schottky Barrier Diode With Low Turn-on Voltage and Leakage Current

This work reports a $\beta $ -Ga2O3 double-barrier Schottky barrier diode (DBSBD) with both low turn-on voltage and low reverse leakage current by using Ni and PtOx as the anode electrode. The barrier height of PtOx-based diode can be effectively modulated from 1.26 to 1.62 eV by adjusting oxygen pressure during sputtering processes. Combining the maximum work function of PtOx electrode with the optimization of the electrode ratio of Ni and PtOx, the DBSBD with an electrode diameter ratio of $\text{D}_{\text {Ni}} /\text{D}_{\text {PtOx}}= {75}/{150} \mu \text{m}$ not only exhibits a high forward current of 470.9 A/cm2 (at 3.5 V), a low on-resistance of 4.1 $\text{m}\Omega ~\cdot $ cm2 and a low turn-on voltage of 1.13 V, but also possesses a relatively low reverse leakage current of ${1.2}\times {10}^{-{7}}$ A/cm2 (at −100 V), which is more than one order of magnitude lower than that of the Ni-SBD. Silvaco TCAD simulation reveals that such optimization can be attributed to the suppression of edge leakage current due to the double-barrier contact. Therefore, the strategy of double-barrier design can balance the forward and reverse characteristics in SBD, providing a new device structure for advanced power electronics.

High Single-Event Burnout Resistance 4H-SiC Junction Barrier Schottky Diode

This paper presents a single-event burnout (SEB) resistance method for 4H-SiC Junction Barrier Schottky Diode (JBS) under high bias voltage and linear energy transfer (LET) conditions. The method is validated via two-dimensional numerical simulations. The analysis and comparison of conventional 4H-SiC JBS and 4H-SiC Multi-Buffer Layer JBS (MBL-JBS) diodes verify the resistance tolerance of the latter device to SEB. Silvaco TCAD simulation results prove that the 4H-SiC MBL-JBS modulates the drift region's electric field distribution and disperses the high-peak electric field at the N-/N+ junction. Moreover, it reduces the impact generation rate at the Schottky, PN and N-/N+ junctions to achieve SEB tolerance. The device's SEB performance is optimized by adjusting the 4H-SiC MBL-JBS structure parameters, and the SEB threshold voltage is significantly improved compared with the traditional structure.

Performance of Ge and In0.53Ga0.47 as Thermophotovoltaic Cells under Different Spectral Irradiances

The investigation on the effect of illumination power intensities for a thermophotovoltaic (TPV) system is crucial to enhance the TPV cell performance. To date, the studies on the effect of illumination intensities were limited to solar photovoltaic cells application. Meanwhile, the reported work on the impact of infrared illumination intensities on TPV cells are done at limited temperatures and intensities. The effects of TPV intensities on all performance parameters are not comprehensively studied and fully elucidated. Therefore, this paper investigates the performance of indirect-bandgap Germanium (Ge) and direct-bandgap Indium Gallium Arsenide (InGaAs) cells under various TPV spectral irradiances. Silvaco TCAD simulation software was used to investigate the effect of blackbody temperatures ranging from 800 to 2000 K with different illumination intensities on the TPV cell performances. It was found that higher conversion efficiencies are achieved for both TPV cells under higher illumination intensities due to the increase in open-circuit voltage and fill factor. As the beam intensity increases for temperatures >1600 K, fill factor slowly increases for the Ge cell, but decreases for the InGaAs cell due to the increase in the $I^{2}R_{s}$ losses associated with the high current. The finding demonstrates that the open-circuit voltage of indirect-bandgap TPV cell is significantly increased with higher illumination intensities. The variations in cells performance are explicitly explained based on factors such as TPV design structure and the physical properties of semiconductor at varying illumination intensities. The performance of both TPV cells were also analyzed at the minimum optical losses. Average efficiencies of Ge and InGaAs TPV cells were increased to 26.05% and 27.92%, respectively, when the optical losses were minimized with anti-reflection coating and thicker absorber layer. The results of this work demonstrate that by detailed consideration of the effect of spectral irradiances, a high-performance TPV system can be developed.

Switching Performance Analysis of 3.5 kV Ga2O3 Power FinFETs

This article presents switching performance analysis of a normally-off 3.5 kV $\beta $ -Ga2O3 power FinFET using Silvaco TCAD simulation platform. The simulated electric field and OFF-state capacitances at a drain voltage ( ${V}_{\text {D}}{)}$ of 3.5 kV were compared for FinFETs with two different structures: (i) 30-nm-thick Al2O3 in the planar regions and partially-filled (PF) inter-fin areas and (ii) 130-nm-thick Al2O3 in the planar regions and fully-filled (FF) inter-fin areas. The FF FinFET showed a smaller OFF-state ${C}_{\text {GS}}$ and ${C}_{\text {GD}}$ and the thicker Al2O3 significantly reduced peak electric field at the corner of the fin. Therefore, via TCAD device-circuit-integrated model, the impact of electron mobility in the MOS channel, bulk fin and drift region, and the substrate thickness on the device switching performances were investigated on a single-fin FF FinFET structure. The device with 100- $\mu \text{m}$ -thick substrate and ideal drift region and fin mobilities of 180 cm2/Vs showed 82.6% improvement in the total switching time and 82.2% lower switching losses compared with the device which had thicker substrate thickness ( $600~\mu \text{m}$ ) and lower electron mobilities in the drift region (130 cm2/Vs), bulk fin (30 cm2/Vs), and MOS channel (2 cm2/Vs). Moreover, the switching performance of multifin FF FinFETs with different fin width/pitch ratio was studied. At a given pitch size of 700 nm, the total power loss of the input power at a frequency of 200 kHz was reduced from 0.83% to 0.61% as pitch ratio reduced from 57.1% to 14.3%. These findings provide helpful insights for design and fabrication of Ga2O3 FinFETs with enhanced switching performance for low-waste power conversion applications.

Understanding Short-Circuit Failure Mechanism of Double-Trench SiC Power MOSFETs

The short-circuit (SC) failure mechanism of double-trench silicon carbide (SiC) power metal-oxide- semiconductor field-effect transistors (MOSFETs) is comprehensively studied and analyzed. Unlike traditional planar-gate devices which die from thermal runaway, the double-trench ones exhibit a different SC failure phenomenon. After enduring an ultimate SC stress cycle, the gate of the double-trench device breaks down while the conducting and blocking characteristics of the body diode remain stable. During the SC process, a substantial negative gate current from the semiconductor side to the poly gate side is observed. Silvaco TCAD simulations demonstrate that ultrahigh current density and impact ionization appear at the gate trench corners simultaneously, driving the generated hot holes through the oxide, forming the negative gate current. The sustained action of this gate current component on the oxide finally results in the failure. Moreover, the influence that bias voltages have on the SC endurance capability of the device is analyzed. In general, the higher the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> are the shorter the SC endurance time will be. It is also found that the double-trench device fails with a higher junction temperature when stressed under a lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> condition, implying that the temperature rarely affects the failure, proving the correctness of the proposed SC failure mechanism.

Enhancing Hot-Carrier Reliability of Dual-Gate Low-Temperature Polysilicon TFTs by Increasing Lightly Doped Drain Length

In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative Vth shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model.

Electrical characteristics analysis of a 314 mm2 double-sided spiral SDD for x-ray pulsar navigation

Pulsar navigation, to meet the physical needs of detecting pulsed x-ray contour, requires a large-area and high-energy resolution silicon drift detector (SDD). Until recently when we designed and fabricated a 314 mm2 double-sided spiral SDD, SDDs developed worldwide have been relatively small in size with a typical diameter less than 10 mm. The details of the design of our 314 mm2 double-sided spiral SDD had been reported in the literature (Li (2013) Nuclear Instruments and Methods in Physics Research A 730 73–78). Present work involves the analysis of electrical characteristics simulations of a 314 mm2 double-sided spiral SDD. It is essential to study the carriers drift behavior of a 314 mm2 double-sided spiral SDD for the structural design optimization of the detector. Therefore, this paper analyzes the relevant electrical characteristics that can characterize the carriers drift behavior. Firstly, this paper illustrates the electric potential, electric field, and electron concentration of the detector. Then, it also provides an analysis of the transient current by simulated the single event transient (SET) effect. The SILVACO TCAD simulator was used to simulate these electrical characteristics. Based on TCAD simulation, the best drift electric field and optimal electron drift channel in a 314 mm2 double-sided spiral SDD are demonstrated. Moreover, the transient current and charge collection mechanism of the detector is also analyzed. Finally, we also tested the leakage current and capacitance of the detector at room temperature.

DC and RF characteristics of 20 nm gate length InAlAs/InGaAs/InP HEMTs for high frequency application

lnAlAs/lnGaAs/InP high electron mobility transistor (HEMT) offers excellent high frequency operation.In this work,the DC and RF performance of a 20 nm gate length enhancement mode InAlAs/InGaAs/InP high electron mobility transistor (HEMT) on InP substrate are presented.The SILVACO-TCAD simulations performed at room temperature using the appropriate model sshowed that the studied device exhibit excellent pinch-off characteristics, with a maximum transconductance of 1100ms/mm, a threshold voltage of 0,62V, and an Ion/Ioff ratio of 2.106. The cut-off frequency and maximum frequency of oscillation are 980 GHz and 1.3THz respectively. These promising results allow us to affirm that this device is intended to be used in high frequency applications.

Design of Strained Ge Schottky Diode on Si Substrate for Microwave Rectifier Circuit

In recent years, wireless energy transmission technology has developed rapidly and has received increasing attention in the industry. For microwave wireless energy transfer system applications, Ge Schottky diodes as the core components of the rectifier circuit are commonly used. Compared with Ge semiconductor, strained Ge semiconductor on Si substrate has the advantages of compatibility with Si process, low cost, and high electron mobility. It is an ideal replacement material for Ge semiconductor applications. In view of this, based on the model of the relationship between the performance of strained Ge semiconductor on Si substrate Schottky diodes and the geometric parameters of the device and the physical parameters of the material, Silvaco TCAD and ADS simulation software are jointly used to propose a novel strained Ge semiconductor on Si substrate Schottky diode for microwave rectification circuit. Simulation results show that the strained Ge semiconductor on Si substrate Schottky diode has a rectification efficiency of 70.1% when the input of the rectifier circuit is 20 dBm, the load resistance is R = 1000 Ω, and the load capacitance is C = 100 pF. Compared with traditional Ge Schottky diodes, this optimal operating point is closer to a low energy density, which is beneficial to a wide range of energy absorption. Studies have shown the feasibility of replacing Ge Schottky diodes. The research in this paper can provide valuable reference for the design and development of the core components of the rectifier circuit of the microwave infinite energy transmission system.

Performance Investigation of Gate Engineered tri-Gate SOI TFETs with Different High-K Dielectric Materials for Low Power Applications

In this article, a three-dimensional model of Tri-gate Tunnel Filed effect transistors (TFET) with different gate materials is proposed. Analysis and comparison of various structures such as single material gate, double material gate and triple material gate of a Tri-gate TFET is performed with respect to both DC and AC characteristics. Various electrical parameters that define the performance of a semiconductor device are verified using Silvaco TCAD Simulation results. Parameters analyzed in this work include surface potential, lateral electric field, total electric field along the channel, drain current, transconductance and output conductance of single material, double material and triple material Tri-gate TFETs. The comparative performance analysis shows a better DC and AC performance for Triple Material Tri-gate TFET (TMTGTFET) in comparison to single material and double material Tri-gate devices. It could be inferred that short channel effects are considerably reduced in a gate engineered Tri-Gate TFET structure and it also shows remarkable improvement in ON current as the current increases 45% for TMTGTFET when compared to a SMTG TFET. To improve the TMTGTFET performance, different dielectric materials are employed for device characteristics.