Silicon Single Electron Transistor Research Articles

Tunable hybrid silicon single-electron transistor–nanoscale field-effect transistor operating at room temperature

A hybrid silicon single-electron transistor (SET)–field-effect transistor (FET), tunable by gate voltages between single-electron and classical FET operation, at room temperature (RT) is demonstrated. The device uses a side-gated, ∼6 nm wide, heavily doped n+ silicon fin. A gate-controlled transition occurs from a depletion mode FET, including characteristic output saturation, to a quantum dot SET with “Coulomb diamond” characteristics above and near the threshold voltage, respectively. Below the threshold voltage, p-FET behavior implies ambipolar operation. Statistics for 180 research devices show a high yield of ∼37% for RT SET–FET operation and mean single-electron addition energy ∼0.3 eV. This yield also demonstrates the probability of single-electron effects in highly scaled doped nanoFETs and the possibility of electrically tunable, RT quantum and classical mode, nanoelectronic circuits.

Novel Hybrid Silicon SETMOS Design for Power Efficient Room Temperature Operation

A novel hybrid silicon Single Electron Transistor Metal Oxide Semiconductor (SETMOS) logic is evaluated for its functionality and usability. Emphasis is given on obtaining functionality at ambient temperature with low power consumption and significant drive. Performance is evaluated with respect to 22 nm Complementary Metal Oxide Semiconductor (CMOS) technology and other popular hybrid SETMOS topologies. The results produced here not only comprehend performance of various SET-CMOS based logic architectures, but they are also closer to real values as they consider effect of parasitic in respective topologies. Proposed work is power efficient, scalable, accurate and process compatible logic design, which uses less hardware and operates at room temperature. It relies on CMOS compatible fabrication of Silicon SET and P-Type Metal Oxide Semiconductor (PMOS) on same chip footprint. When compared with contemporary SETMOS hybrid circuits, it offers 90.29 % power improvement at the cost of 16.53 % reduction in speed.

Interplay between mutual capacitive coupling and tunneling in silicon single electron transistor coupled to dopant atom

Interplay between mutual capacitive coupling and tunneling in silicon single electron transistor coupled to dopant atom

A Compact Model Based on Bardeen’s Transfer Hamiltonian Formalism for Silicon Single Electron Transistors

Presented is a physics-based compact model for a silicon-nanopillar single-electron transistor (SET). Tunneling currents are calculated using a master equation approach with rates obtained via the transfer Hamiltonian formalism. The quantum confinement of electrons on the quantum dot is taken into consideration by a suitable approximation as required for a nanometer-sized device. Device geometry and material properties enter the model directly as model parameters. Thus, this model enables the investigation of circuits and application scenarios for specific SET technologies in dependence on geometry and material variations. The model was implemented in HSPICE and used to simulate an inverter and a ring oscillator to evaluate the performance of the model. Specific device characteristics for a SET with a semiconducting quantum dot like the gate voltage threshold for the onset of current oscillations are reproduced. Therefore, simulations with the presented model will allow the testing of the SET circuits with more realistic assumptions concerning the device behavior compared to the much more abstract SET compact models available up to now.

Sequential reduction of the silicon single-electron transistor structure to atomic scale

Here we present an original CMOS compatible fabrication method of a single-electron transistor structure with extremely small islands, formed by solitary phosphorus dopants in the silicon nanobridge. Its key feature is the controllable size reduction of the nanobridge in sequential cycles of low energy isotropic reactive ion etching that results in a decreased number of active charge centers (dopants) in the nanobridge from hundreds to a single one. Electron transport through the individual phosphorous dopants in the silicon lattice was studied. The final transistor structure demonstrates a Coulomb blockade voltage of ∼30 mV and nanobridge size estimated as . Analysis of current stability diagrams shows that electron transport in samples after the final etching stage had a single-electron nature and was carried through three phosphorus atoms. The fabrication method of the demonstrated structure allows it to be modified further by various impurities in additional etching and implantation cycles.

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors

Single nanometre scale quantum dots (QDs) have significant potential for many ‘beyond CMOS’ nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ∼0.8 eV, and a quantum confinement energy ∼0.3 eV, are observed, implying a QD only ∼1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, ‘beyond CMOS’ RT QD transistors can be produced using current ‘conventional’ semiconductor device fabrication techniques.

Pattern-generation and pattern-transfer for single-digit nano devices

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

A sensitive charge scanning probe based on silicon single electron transistor**Project supported by the Instrument Developing Project of the Chinese Academy of Sciences (No. YZ201152), the National Natural Science Foundation of China (No. 11403084), the Fundamental Research Funds for Central Universities (Nos. JUSRP51510, JUDCF12032), and the Graduate Student Innovation Program for Universities of Jiangsu Province (No. CXLX12_0724).

Single electron transistors (SETs) are known to be extremely sensitive electrometers owing to their high charge sensitivity. In this work, we report the design, fabrication, and characterization of a silicon-on-insulator-based SET scanning probe. The fabricated SET is located about 10 μm away from the probe tip. The SET with a quantum dot of about 70 nm in diameter exhibits an obvious Coulomb blockade effect measured at 4.1 K. The Coulomb blockade energy is about 18 meV, and the charge sensitivity is in the order of 10−5−10−3 e/Hz1/2. This SET scanning probe can be used to map charge distribution and sense dynamic charge fluctuation in nanodevices or circuits under test, realizing high sensitivity and high spatial resolution charge detection.

Direct detection of a transport-blocking trap in a nanoscaled silicon single-electron transistor by radio-frequency reflectometry

The continuous downscaling of transistors results in nanoscale devices which require fewer and fewer charged carriers for their operation. The ultimate charge controlled device, the single-electron transistor (SET), controls the transfer of individual electrons. It is also the most sensitive electrometer, and as a result the electron transport through it can be dramatically affected by nearby charges. Standard direct-current characterization techniques, however, are often unable to unambiguously detect and resolve the origin of the observed changes in SET behavior arising from changes in the charge state of a capacitively coupled trap. Using a radio-frequency (RF) reflectometry technique, we are able to unequivocally detect this process, in very close agreement with modeling of the trap's occupation probability.

Peak position control of Coulomb blockade oscillations in silicon single-electron transistors with floating gate operating at room temperature

A silicon single-electron transistor (SET) with a floating gate (FG) that covers the entire SET structure is proposed and fabricated to study a nonvolatile and precise peak shift of Coulomb blockade oscillations. Large Coulomb blockade oscillations with a peak-to-valley current ratio as high as 14.1, a parallel peak position control without a change in peak height, and a long retention time of over one month are successfully demonstrated at room temperature. The proposed FG SET is suitable for hybrid SET/CMOS circuits for adding more functionalities into future very large scale integration (VLSI) devices.

Probing a single nuclear spin in a silicon single electron transistor

We study single electron transport across a single Bi dopant in a silicon nanotransistor to assess how the strong hyperfine coupling with the Bi nuclear spin I = 9/2 affects the transport characteristics of the device. In the sequential tunneling regime we find that at, temperatures in the range of 100 mK, dI/dV curves reflect the zero field hyperfine splitting as well as its evolution under an applied magnetic field. Our non-equilibrium quantum simulations show that nuclear spins can be partially polarized parallel or antiparallel to the electronic spin just tuning the applied bias.

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm2 is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.

A hybrid double-dot in silicon

We report electrical measurements of a single arsenic dopant atom in the tunnel barrier of a silicon single-electron transistor (SET). In addition to performing the electrical characterization of the individual dopant, we study the series electrical transport through the dopant and SET. We measure the triple points of this hybrid double-dot, using simulations to support our results, and show that we can tune the electrostatic coupling between the two sub-systems.

Microwave driven arbitrary coupling between trapped charge resonances in a silicon single electron transistor

We report controllable coupling between coherent excitations in a silicon transistor, which is useful for double-qubit gate operation. Coupling interactions may be directed by adjusting the gate voltage in a semiconductor device or by an additional flux in a superconducting device. Here, we demonstrate an alternative approach to coupling by exploiting the nonlinear behavior of the silicon transistor. Microwave spectroscopy on a DC-biased transistor has previously been found to indicate the presence of coherent oscillating electrons. We couple two such resonances by using triple-frequency spectroscopy, where the third frequency corresponds to the frequency difference between the two on-resonance frequencies.

Defect detection in nano-scale transistors based on radio-frequency reflectometry

Radio-frequency reflectometry in silicon single-electron transistors (SETs) is presented. At low temperatures (&amp;lt;4 K), in addition to the expected Coulomb blockade features associated with charging of the SET dot, quasi-periodic oscillations are observed that persist in the fully depleted regime where the SET dot is completely empty. A model, confirmed by simulations, indicates that these oscillations originate from charging of an unintended floating gate located in the heavily doped polycrystalline silicon gate stack. The technique used in this experiment can be applied for detailed spectroscopy of various charge defects in nanoscale SETs and field effect transistors.

Fabrication of hybrid metal island/silicon single electron transistor

A novel process for silicon single electron transistors (Si-SET) is presented, combining chemical mechanical polishing (CMP) with the advantages of silicon processing. To eliminate effects caused by random distribution of dopants in the island, The Si-SET’s doped-Si island is replaced with an aluminum or tantalum island by integrating a metal CMP technique with our nano-encapsulation process. The fabricated hybrid Al-island Si-SET has ∼10 nm silicon on insulator lines as the source and drain leads. It shows characteristic Coulomb blockade oscillations with a charging energy of ∼4 meV. The fabrication results demonstrate the scalability of the SET island and the tunnel junction size in a manufacturable top-down approach.

Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices’ Variability?

It is very important to study variability of nanodevices because the inability to produce large amounts of identical nanostructures is eventually a bottleneck for any application. In fact variability is already a major concern for CMOS circuits. In this work we report on the variability of dozens of silicon single-electron transistors (SETs). At room temperature their variability is compared with the variability of the most advanced CMOS FET i.e. the ultra thin Silicon-on-Insulator Multiple gate FET (UT SOI MuGFET). We found that dopants diffused from Source –Drain into the edge of the undoped channel are the main source of variability. This emphasizes the role of extrinsic factors like the contact junctions for variability of any nanodevice.

Microwave-assisted transport via localized states in degenerately doped Si single electron transistors

Resonant microwave-assisted and dc transport are investigated in degenerately doped silicon single electron transistors. A model based on hopping via localized impurity states is developed and first used to explain both the dc temperature dependence and the ac response. In particular, the non-monotonic power dependence of the resonant current under irradiation is proved to be consistent with spatial Rabi oscillations between these localized states.

Electron tunnel rates in a donor-silicon single electron transistor hybrid

We investigate a hybrid structure consisting of $20\pm4$ implanted $^{31}$P atoms close to a gate-induced silicon single electron transistor (SiSET). In this configuration, the SiSET is extremely sensitive to the charge state of the nearby centers, turning from the off state to the conducting state when the charge configuration is changed. We present a method to measure fast electron tunnel rates between donors and the SiSET island, using a pulsed voltage scheme and low-bandwidth current detection. The experimental findings are quantitatively discussed using a rate equation model, enabling the extraction of the capture and emission rates.

Charge sensing in intrinsic silicon quantum dots

We report charge sensing measurements on a silicon quantum dot with a nearby silicon single electron transistor (SET) acting as an electrometer. The devices are electrostatically formed in bulk silicon using surface gates. We show that as an additional electron is added onto the quantum dot, a charge is induced on the SET of approximately 0.2e. These measurements are performed in the many electron regime, where we can count in excess of 20 charge additions onto the quantum dot.