Sequential reduction of the silicon single-electron transistor structure to atomic scale

Abstract

Here we present an original CMOS compatible fabrication method of a single-electron transistor structure with extremely small islands, formed by solitary phosphorus dopants in the silicon nanobridge. Its key feature is the controllable size reduction of the nanobridge in sequential cycles of low energy isotropic reactive ion etching that results in a decreased number of active charge centers (dopants) in the nanobridge from hundreds to a single one. Electron transport through the individual phosphorous dopants in the silicon lattice was studied. The final transistor structure demonstrates a Coulomb blockade voltage of ∼30 mV and nanobridge size estimated as . Analysis of current stability diagrams shows that electron transport in samples after the final etching stage had a single-electron nature and was carried through three phosphorus atoms. The fabrication method of the demonstrated structure allows it to be modified further by various impurities in additional etching and implantation cycles.