Abstract
Presented is a physics-based compact model for a silicon-nanopillar single-electron transistor (SET). Tunneling currents are calculated using a master equation approach with rates obtained via the transfer Hamiltonian formalism. The quantum confinement of electrons on the quantum dot is taken into consideration by a suitable approximation as required for a nanometer-sized device. Device geometry and material properties enter the model directly as model parameters. Thus, this model enables the investigation of circuits and application scenarios for specific SET technologies in dependence on geometry and material variations. The model was implemented in HSPICE and used to simulate an inverter and a ring oscillator to evaluate the performance of the model. Specific device characteristics for a SET with a semiconducting quantum dot like the gate voltage threshold for the onset of current oscillations are reproduced. Therefore, simulations with the presented model will allow the testing of the SET circuits with more realistic assumptions concerning the device behavior compared to the much more abstract SET compact models available up to now.
Highlights
The miniaturization of conventional silicon CMOS electronics is approaching physical limits that make it increasingly difficult to follow the so-called More-Moore pathway
A HSPICE simulation shown in Fig. 2 using Inokawa’s single-electron transistor (SET) model [6], with capacitances and tunneling resistances calibrated to numerical simulation, exhibits good agreement in the Coulomb-Blockade regime while the other operation regimes are not well described or not featured at all
A compact model for the physical description of a SET with silicon quantum dot (QD) is derived from basic principles and tested against numerical simulations
Summary
The miniaturization of conventional silicon CMOS electronics is approaching physical limits that make it increasingly difficult to follow the so-called More-Moore pathway. Due to the fundamentally different mode of operation of a SET compared to a classical transistor like a MOSFET when making use of the Coulomb blockade effect, the applicability of SETs in electronic circuits must be thoroughly tested by simulation. This requires the availability of suitable compact models that allow fast evaluation of the current-voltage (IV) behavior and usage in a circuit simulator for the coupling with other circuit elements. Numerical simulations of SET characteristics based on three-dimensional device geometries and using the transfer Hamiltonian method proposed by Bardeen [23] for current calculation have been reported beforehand [24]–[27]. The model and its ability to reproduce the correct trends for geometric variations are demonstrated via numerical simulations with the framework described in [27]
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