Novel Hybrid Silicon SETMOS Design for Power Efficient Room Temperature Operation

Abstract

A novel hybrid silicon Single Electron Transistor Metal Oxide Semiconductor (SETMOS) logic is evaluated for its functionality and usability. Emphasis is given on obtaining functionality at ambient temperature with low power consumption and significant drive. Performance is evaluated with respect to 22 nm Complementary Metal Oxide Semiconductor (CMOS) technology and other popular hybrid SETMOS topologies. The results produced here not only comprehend performance of various SET-CMOS based logic architectures, but they are also closer to real values as they consider effect of parasitic in respective topologies. Proposed work is power efficient, scalable, accurate and process compatible logic design, which uses less hardware and operates at room temperature. It relies on CMOS compatible fabrication of Silicon SET and P-Type Metal Oxide Semiconductor (PMOS) on same chip footprint. When compared with contemporary SETMOS hybrid circuits, it offers 90.29 % power improvement at the cost of 16.53 % reduction in speed.