Silicon Oxynitride Gate Research Articles

Normally-Off GaN-on-Si MISFET Using PECVD SiON Gate Dielectric

We have developed a silicon oxynitride (SiON) deposition process using a plasma-enhanced chemical vapor deposition system for the gate dielectric of GaN-on-Si metal-insulator-semiconductor field-effect transistors (MISFETs). The optimized SiON film had a relative dielectric constant of 5.3 and a breakdown field of 12 MV/cm. A normally-off GaN-on-Si MISFET fabricated with a 33-nm SiON gate dielectric exhibited a threshold voltage of ~2 V, an ON-resistance of 7.85 mQ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and a breakdown voltage of ~640 V at the OFF-state current density of 1 μA/mm. The extracted interface trap density was 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> · eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> - E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> = 0.442 eV, which resulted in negligible hysteresis and excellent dynamic characteristics.

Impact of oxygen plasma on nitrided and annealed atomic layer deposited SiO2/high-k/metal gate for high-voltage input and output fin-shaped field effect transistor devices

In this study, the authors investigate the impact of radical oxygen plasma on nitrided and annealed atomic layer deposited (ALD) SiO2 as a thick gate oxide (1.65–3 V) with a high-k/metal gate transistor. Time-dependent-dielectric-breakdown voltage, secondary ion mass spectroscopy (SIMS), and x-ray photoelectron spectroscopy (XPS) studies were conducted, and the results are discussed for nitrided and annealed ALD SiO2 with and without radical oxygen plasma exposure. Atomistic material simulations were performed to understand the reactions between oxygen radicals and silicon oxynitride (SiON). Our key findings from SIMS and XPS show that radical oxygen plasma exposure led to a 34% nitrogen loss from the thick SiON gate oxide and damaged the gate oxide, resulting in a 1 V reduction in the dielectric breakdown voltage. Atomistic material simulation results also show that atomic oxygen can react with Si-(ON)-Si to form Si–O–Si bonds and mobilize NO into the interstitial space. Similarly, when O atoms and O2 molecules are placed near N clusters, spontaneous diffusion of N2 into the interstitial space occurs. Diffusion barrier calculations further indicate a barrier energy of less than 0.5 eV in SiO2 and SiON, which can lead to the out-diffusion of NO and N2 from SiO2 and SiON. These compositional changes may result in increased leakage and a degraded breakdown voltage. The increased gate leakage and degraded breakdown voltage is attributed to the compositional changes in SiON.

Total ionizing dose-hardened carbon nanotube thin-film transistors with silicon oxynitride gate dielectrics

We investigate the radiation response of single-walled carbon nanotube (SWCNT) thin-film transistors fabricated with 23 nm silicon oxynitride gate dielectric layers, for total ionizing doses (TIDs) of Co-60 gamma irradiation up to 2 Mrad(Si). Irradiations with ±1 MV/cm across the gate dielectric have little effect on the threshold voltage, yielding shifts of less than ±0.25 V and no detrimental effect on SWCNT mobility or maximum drain current. This illustrates the need to consider the total device material composition when investigating the radiation response of carbon nanoelectronics and substantiates the applicability of SWCNT-based nanoelectronics for use in high TID environments.

Comparative studies of Ge and Si p-channel metal–oxide–semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal–oxide–semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance–voltage curve hysteresis of Ge metal–oxide–semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.

Hot-Carrier Immunity of Polycrystalline Silicon Thin Film Transistors Using Silicon Oxynitride Gate Dielectric Formed with Plasma-Enhanced Chemical Vapor Deposition

An analysis is presented of the hot-carrier degradation in a polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon oxynitride gate dielectric formed with plasma-enhanced chemical vapor deposition. An introduction of silicon oxynitride into a gate dielectric significantly improves hot-carrier immunity even under the severe stressing mode of drain avalanche hot carriers. To compensate the initial negative shift of threshold voltage for TFTs with a silicon oxynitride gate dielectric, high-pressure water vapor annealing (HWA) is applied. A comparison of TFTs with and without HWA reveals that the improvement in hot-carrier immunity is mainly attributed to the introduction of Si≡N bonds into a gate dielectric.

Material Dependence of Negative Bias Temperature Instability (NBTI) Stress and Recovery in SiON p-MOSFETs

Negative Bias Temperature Instability (NBTI) is studied in Silicon Oxynitride (SiON) p-MOSFETs using a recently developed Ultra-Fast On-The-Fly linear drain current method. It is shown that both stress and recovery phases of NBTI are strongly influenced by SiON gate insulator process. Gate insulator nitrogen spatial distribution is shown to impact interface trap generation (NIT) and hole trapping (Nh) components of overall threshold voltage shift (VT). A simple, self consistent method is proposed to isolate NIT and Nh. It is shown that the time dynamics of stress and recovery phases are strongly correlated, at short time governed by trapping and detrapping of holes, and at long time by generation and passivation of interface traps.

The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly $I_{\rm DLIN}$ Technique

Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DLIN</sub> technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface.

Comparison of leakage behaviors in p- and n-type metal-oxide-semiconductor capacitors with hafnium silicon oxynitride gate dielectric by electron-beam-induced current

The gate leakage behaviors of p- and n-type metal-oxide-semiconductor (p−∕nMOS) capacitors with hafnium silicon oxynitride (HfSiON) gate dielectric were microscopically investigated by electron-beam-induced current (EBIC) technique. Carrier separated EBIC measurement has found that in nonstressed samples, hole conduction in pMOS is significantly enhanced by trap-assisted tunneling, while electron conduction in nMOS is independent of traps. After voltage stress, traps are induced in nMOS and enhanced electron conduction.

Electrical method of measuring physical thickness and nitrogen concentration of silicon oxynitride gate dielectric for MOSFETs

This paper proposes an electrical method of measuring the physical thickness T ox and the nitrogen concentration α N of the silicon oxynitride (SiON) gate dielectric for MOSFETs. The proposed method uses the facts that the gate dielectric breakdown field strength E BD depends on α N for a given T ox and the direct tunneling (DT) current depends strongly on T ox. Gate current I g versus gate voltage V g ( I g– V g) curves at a given α N were calculated for different T oxs using the DT model, and measurements were compared to the curves to obtain T ox. The α N was obtained by comparing the measured E BD at a given T ox with the theoretical E BD for a SiON gate dielectric. These two steps were iterated until the convergence error of α N was less than 1%. The I g– V g curves calculated using the extracted T oxs and α Ns agreed very well with measurements when V g was less than the gate breakdown voltage. The difference between the equivalent oxide thickness (EOT) measured using the C– V method and the EOT calculated using the extracted T ox and α N was less than 7%, demonstrating that the proposed method can accurately determine T ox and α N of an ultra-thin SiON gate dielectric from only the measured I g– V g curve of the MOSFET.

Observation of leakage sites in a hafnium silicon oxynitride gate dielectric of a metal-oxide-semiconductor field-effect transistor device by electron-beam-induced current

Leakage sites in hafnium silicon oxynitride gate dielectrics of metal-oxide-semiconductor field-effect transistors were directly identified by means of electron-beam-induced current (EBIC) technique. Leakage sites were observed as bright spots mostly on the periphery of gate. With the gate bias increasing, the EBIC current of bright spots increased exponentially, but the number of bright spots did not increase.

Effect of thickness on the crystallization of ultrathin HfSiON gate dielectrics

The crystallization of ultrathin hafnium silicon oxynitride (HfSiON) gate dielectric is studied as a function of physical thickness. Grazing incidence x-ray diffraction (GI-XRD) was used to detect phase separation and crystallization of 1.5, 2.0, 2.5, and 4.0 nm HfSiON films after 1000°C10s dopant activation anneal. Crystallization peaks corresponding to monoclinic and tetragonal HfO2 were detected in 2.5 and 4.0 nm HfSiON films. These GI-XRD results were supported by plan-view transmission electron microscopy images of the HfSiON films. Film crystallinity seems to impact voltage instability in thicker HfSiON films.

Time-dependent degradation due to negative bias temperature instability of p-MOSFET with an ultra-thin SiON gate dielectric

This paper presents the time-dependence of the negative bias temperature instability (NBTI) degradation of p-MOSFETs with an ultra-thin silicon oxynitride gate dielectric. The concentrations of nitrogen in the gate dielectric were approximately 3% and 10%. The device with 10% nitrogen concentration had unique time-dependent degradation characteristics due to the nitrogen enhanced NBTI effect. It degraded significantly just after application of an NBTI stress. After this initial degradation, a fast and slow degradation followed in sequence. The initial, fast, and slow degradations appear to be associated with the deep donor effect of nitrogen, the diffusion of ionic and neutral hydrogen combined with Si–H bond breaking, and the diffusion of neutral hydrogen combined with O–H bond breaking, respectively. Owing to the slow down of the NBTI degradation after the initial and fast degradations, the lifetime for the device with 10% nitrogen concentration was three times longer than that with 3% nitrogen concentration.

Ultrascaled hafnium silicon oxynitride gate dielectrics with excellent carrier mobility and reliability

A hafnium silicon oxynitride gate dielectric with a universal channel mobility of ∼90% at 1MV∕cm, equivalent oxide thickness of approximately 1nm, and leakage current 200× less than SiO2 is reported. X-ray photoelectron spectroscopy results suggest that the small peak mobility loss observed in scaled HfSiON may be attributed to increased Si–N bonding near the silicon interface. In accordance with these mobility results, the Si–N:Hf–N bond ratio decreases with increasing HfSiON physical thickness. Threshold voltage instability at 1nm equivalent oxide thickness is less than 10mV after a 1000s stress at 22MVcm. ΔVTH monotonically increases with HfSiON physical thickness. This is associated with greater crystallization in thicker HfSiON films.

Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode

In this work, the effective mobility in n- and p-channel FinFETS with silicon oxynitride and HfO2 gate dielectrics and TaN gate electrode is studied as a function of the inversion charge density using a split C-V technique. The mobility behavior in narrow-fin devices is compared to that in quasi-planar wide-fin devices, and the mechanisms responsible for the observed differences are discussed. The devices with HfO2 and silicon oxynitride gate dielectrics exhibit similar mobility behavior.

Model to Predict Gate Tunneling Current of Plasma Oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.

Abnormal enhancement of interface trap generation under dynamic oxide field stress at MHz region

By stressing metal-oxide-semiconductor field-effect transistors with ultrathin silicon dioxide or oxynitride gate dielectrics under square wave form voltage at the MHz region, an abnormal enhancement of interface trap generation in the midchannel region has been observed at some special frequencies. A hypothesis, including self-accelerating interface trap generation originated from the positive feedback of a charge pumping current to be contributed by the stress-induced near-interface oxide traps and a resonant tunneling via the near interface oxide trap states at those frequencies, is proposed to explain the observed phenomenon.

First-Principles-Calculation Method for Optimizing Strain to Reduce Gate Leakage Current in MOS Transistors with Silicon Oxynitride Gate Dielectrics

We developed a method for optimizing strain to reduce gate leakage current in metal-oxide-semiconductor (MOS) transistors by using first-principles calculations. This method was used to investigate the possibility of decreasing gate leakage current by controlling the strain on gate dielectric materials. We found that tensile strain increases the leakage current through both silicon oxide (SiO2) and silicon oxynitride (SiON) gate dielectrics, whereas compressive strain hardly changes the leakage current through SiO2 gate dielectrics and decreases the leakage current through SiON gate dielectrics. These changes reflect strain-induced changes in the band gaps of these materials. Using finite element analysis to estimate the strain in MOS transistors, we showed the usability of SiON in terms of gate leakage currents and the importance of controlling the strain on the gate dielectric materials.

Temperature-accelerated breakdown in ultra-thin SiON dielectrics

The temperature-dependent breakdown of silicon oxynitride gate dielectrics was studied to determine their reliability at and above operating temperatures. This paper demonstrates that the Weibull slopes of the ultra-thin layers are temperature dependent in the range from room temperature to 200 °C, and furthermore different behaviour is observed for pmos and nmos structures, with pmos structures not suffering any reliability loss at elevated temperature. We highlight that the improved reliability may simply be related to the problem of detecting the ‘real’ breakdown in the layers. Further to this we find an interesting effect where temperature and voltage can be used interchangeably to stress an oxide, and propose a method of normalizing stress data collected at a number of stress temperatures to one reference temperature. The findings support a voltage-dependent voltage acceleration.

Weibull slope and voltage acceleration of ultra-thin (1.1–1.45 nm EOT) oxynitrides

The reliability of ultra-thin silicon oxynitride gate dielectrics was investigated in terms of the Weibull slope of the t bd distributions, and the voltage acceleration factor. High field t BD statistics were extrapolated using a worst-case linear fit, to the low field region. The samples showed low voltage acceleration, which degrades reliability, but this is overcome by high Weibull slopes ( β), which improve reliability. The high β values were investigated by monitoring the change in β as gate current increased during CVS. We saw the Weibull slope change from ≈1 at low current to 2 at high current, indicating that breakdown results from 2-trap conduction. Charge pumping measurements showed that the trap generation rate at the SiON/Si interface, where most of the Nitrogen resides was very low. Thus it was concluded that there is a much higher trap generation rate in the bulk than at the interface and this is responsible for the values of β.