Silicon-on-insulator Substrate Research Articles

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Partially depleted SOI MOSFET is now the mainstream technology adopted by all major foundries and fabless companies for the design of several wireless sub-systems. Today, more than 95 percent of substrates used in fabricating cellular and connectivity switches for handsets are SOI (from Navian market analyst, 2016 report) whereas it was not even in production in 2008, GaAs being mainstream at that time. Beside main switch, front-end module complexity has increased drastically: more than ten integrated switches are required in 4G Tier 1 phones, plus antenna tuners as well as Low Noise Amplifiers (LNA). RF-SOI Power Amplifiers (PA) market adoption is slowly ongoing being mainly position on entry market favoring price-performance-integration trade-off. The concept of trap-rich SOI substrate proposed in 2005 is at the origin of the RF-SOI success story. Indeed, substrate losses and crosstalk were the remaining killer features of Si-based technologies for RF applications these last decades. Thanks to the introduction of a high density of defects called traps at the buried oxide (BOX) / Si handle substrate interface, it has been possible to manufacture high-resistivity (HR) SOI substrates characterized with an effective resistivity as high as 10 kΩ.cm. Those traps originate from the grain boundaries in a thin (less than 1 µm-thick) polysilicon layer. This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along coplanar waveguide (CPW) transmission lines and purely capacitive crosstalk similarly to quartz substrate. It has been shown that the presence of a trapping layer does not alter the DC or RF behavior of SOI MOS transistors. And more importantly, it has been demonstrated that harmonics level originated from the substrate is reduced by at least 20 dB moving from standard resistivity SOI substrate (~ 10 Ω.cm) to high resistivity SOI (~ 1 kΩ.cm), and an additional drop of 40 dB is achieved with the innovative trap-rich HR SOI substrate. The low harmonic level achieved is comparable with insulating substrate. The improvement of the HR SOI substrate with the introduction of defects brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors, tunable MEMS (microelectromechanical systems) capacitors, as well as for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc. Université catholique de Louvain and Soitec have been working together to manufacture the trap-rich SOI substrate concept to further improve the high-frequency performance of commercially available HR-SOI substrates. In 2013, Soitec has unveiled a new flavor of HR-SOI called RF-eSITM-SOI, for enhanced Signal IntegrityTM substrate with a measured effective resistivity as high as 10 kΩ.cm. RF-eSI-SOI substrate can really be considered as a lossless Si-based substrate. Beyond switch, RF-eSI-SOI technology opens the path to further system integration in the Front-End Module (FEM) space as well as even more complex mixed signal System-on-Chip. Based on its 45 nm baseline SOI process, GlobalFoundries just released a RF-SOI mmW offering targeting applications like 5G, satellite communication, automotive radar, WiGig, backhaul. The SOI substrates roadmap for RF and millimeter-waves applications will be presented. Future generations of mobile communication systems such as 5G or the Internet-of-Things will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. Their analog/RF behavior will be described and compared in the paper. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances. The relative impact of the transistor characteristics and the substrate properties on different RF ICs performances will be presented. As it will be demonstrated, the use of specific RF test structures at the early stage of a technological node development is of first importance to analyze the transistor parasitic resistances and capacitances, the transistor cutoff frequencies, the self-heating, and the substrate coupling and non-linear behavior.

Hot-carrier-induced current capability degradation and optimization for lateral IGBT on thick SOI substrate

In this paper, the hot-carrier-induced current capability degradation of a 600 V lateral insulated gate bipolar transistor (LIGBT) on thick silicon on insulator (SOI) substrate is investigated. Our experiments found that, for the SOI-LIGBT, the worst stress condition is the maximum gate voltage (Vgmax) condition and the current degradation is dominated by the damages in the channel region under the Vgmax stress condition. However, further analyses show that the influence of channel region damages on the collector current degradation increases with the increase of measured collector voltage and is maximum in the current saturation region. Therefore, in our opinion, the hot-carrier-induced current capability degradation of the SOI-LIGBT should be evaluated by the degradation of saturation current under the Vgmax stress condition. In addition, a novel SOI-LIGBT structure with an external p-type region was also proposed, which can alleviate the damage in the channel region by reducing the lateral electric field peak. Our experimental results demonstrate that the proposed structure could optimize the hot-carrier reliability effectively with the other characteristics maintained.

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Radio Frequency (RF) Silicon-on-Insulator (SOI) is today a mainstream technology for several front-end module integrated circuits. The high quality of the trap-rich SOI substrate in terms of low insertion loss and high linearity is at the origin of its commercial success. Partially depleted SOI transistors characterized with a channel length from 180 nm down to 45 nm are currently manufactured on top of the trap-rich substrate. However, there is a growing interest for moving from partially to fully depleted SOI transistors in order to improve the RF and millimeter-waves performance of the transistor at low power consumption. On-going research explores the possibility of combining the best of the digital FD SOI devices and high quality RF SOI substrate to design low power mixed-mode communication system-on-chip.

InGaN/GaN micro mirror with electrostatic comb drive actuation integrated on a patterned silicon-on-insulator wafer.

A double-sided mask process is used to define the micro actuators on a silicon-on-insulator (SOI) wafer. Then, an InGaN/GaN multilayer film was deposited on the surface of the above patterned SOI substrate by employed MBE technology. Thus, the final device consisting of comb-drive actuators, springs and micro-mirror is implemented to obtain the two-dimensional (2D) tuning effect of the mirror. The displacement response is characterized by applying voltage to the micro actuators. It shows an approximation linear relationship between the displacement and the square of applied voltage. And the influences of the cross-axis coupling effect are also measured and evaluated. Moreover, the luminous performances of the InGaN/GaN multiquantum well films were also studied by analyzing temperature-dependent and laser intensity-dependent PL spectra. The authors observed the localized state effect and/or band-gap narrowing effect which results in an S-shaped behavior with increasing temperature. The PL intensity and wavelength are also significantly affected by the excitation energy of laser.

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

An optofluidic metasurface for lateral flow-through detection of breast cancer biomarker

The rapid growth of point-of-care tests demands for biosensors with high sensitivity and small size. This paper demonstrates an optofluidic metasurface that combines silicon-on-insulator (SOI) nanophotonics and nanofluidics to realize a high-performance, lateral flow-through biosensor. The metasurface is made of a periodic array of silicon nanoposts on an SOI substrate, and functionalized with specific receptor molecules. Bonding of a polydimethylsiloxane slab directly onto the surface results in an ultracompact biosensor, where analyte solutions are restricted to flow only in the space between the nanoposts. No flow exists above the nanoposts. This sensor design overcomes the issue with diffusion-limited detection of many other biosensors. The lateral flow-through feature, in conjunction with high-Q resonance modes associated with optical bound states of the metasurface, offers an improved sensitivity to subtle molecule-bonding induced changes in refractive index. The device exhibits a resonance mode around 1550 nm wavelength and provides an index sensitivity of 720 nm/RIU. Biosensing is conducted to detect the epidermal growth factor receptor 2 (ErbB2), a protein biomarker for early-stage breast cancer screening, by monitoring resonance wavelength shifts in response to specific analyte-ligand binding events at the metasurface. The limit of detection of the device is 0.7 ng mL−1 for ErbB2.

SOI MESFETs on high-resistivity, trap-rich substrates

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5–10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ∼30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Ferroelectric HfZrOx FETs on SOI Substrate With Reverse-DIBL (Drain-Induced Barrier Lowering) and NDR (Negative Differential Resistance)

Ferroelectric-Hf1−xZrxO2 FETs on silicon on insulator (SOI) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis ( $V_{T}$ -shift), which is based on the capacitance matching concept. The minimum reverse SS = 45 mV/dec and 52 mV/dec are obtained experimentally for SOI and bulk-Si, respectively. The steep SS range (<60 mV/dec) is extended from ~2.5 (bulk-Si) decades to ~3.5 decades SOI. Reverse-drain-induced barrier lowering and negative differential resistance are confirmed at subthreshold region and weak inversion region, respectively.

A SPDT RF Switch Small- and Large-Signal Characteristics on TR-HR SOI Substrates

This paper evaluates the small- and large-signal characteristics of a single pole double thru (SPDT) RF antenna switch including its insertion loss, isolation, and nonlinear behavior. It is fabricated on three different types of high resistivity (HR) silicon-on-insulator (SOI) substrates: one standard (HR-SOI) and two trap-rich (RFeSI80 and RFeSI90). Using a special test structure, the contribution of substrate and active devices is separated for both in small- and large-signal. It is shown that by using trap-rich substrate technology, a reduction of over 16 dB of 2nd harmonic is achieved compared with HR SOI substrate. In off-state, it is shown that 35 dB increase of harmonic level is due to the nonlinearity of active devices. The effect of body bias on small- and large-signal FoMs of the SPDT is investigated and discussed. It is illustrated that trap-rich HR-SOI substrates having much thinner BOX, still outperform classical HR-SOI wafer.

A grating coupler with a trapezoidal hole array for perfectly vertical light coupling between optical fibers and waveguides

A grating coupler with a trapezoidal hole array was designed and fabricated for perfectly vertical light coupling between a single-mode optical fiber and a silicon waveguide on a silicon-on-insulator (SOI) substrate. The grating coupler with an efficiency of 53% was computationally designed at a 1.1-µm-thick buried oxide (BOX) layer. The grating coupler and silicon waveguide were fabricated on the SOI substrate with a 3.0-µm-thick BOX layer by a single full-etch process. The measured coupling efficiency was 24% for TE-polarized light at 1528 nm wavelength, which was 0.69 times of the calculated coupling efficiency for the 3.0-µm-thick BOX layer.

Photonic crystal bandedge membrane lasers on silicon.

We report here the design and experimental demonstration of optically pumped photonic crystal bandedge membrane lasers on silicon-on-insulator (SOI) and on bulk silicon (Si) substrates, based on heterogeneously integrated InGaAsP multi-quantum-well membrane layers transfer printed onto patterned photonic crystal cavities. Single-mode lasing under room-temperature operation was observed at 1542nm, with excellent side mode suppression ratio greater than 31.5dB, for the laser built on SOI substrate. For the laser built on bulk Si substrate, single-mode lasing was also achieved at 1452nm with much lower thermal resistance, as compared to that of the laser built on SOI substrates. Such improved thermal characteristics are favorable for lasers operating potentially at higher temperatures and higher power.

Novel nanofluidic chemical cells based on self-assembled solid-state SiO2 nanotubes

Novel nanofluidic chemical cells based on self-assembled solid-state SiO2 nanotubes on silicon-on-insulator (SOI) substrate have been successfully fabricated and characterized. The vertical SiO2 nanotubes with a smooth cavity are built from Si nanowires which were epitaxially grown on the SOI substrate. The nanotubes have rigid, dry-oxidized SiO2 walls with precisely controlled nanotube inner diameter, which is very attractive for chemical-/bio-sensing applications. No dispersion/aligning procedures were involved in the nanotube fabrication and integration by using this technology, enabling a clean and smooth chemical cell. Such a robust and well-controlled nanotube is an excellent case of developing functional nanomaterials by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth. These solid, smooth, clean SiO2 nanotubes and nanofluidic devices are very encouraging and attractive in future bio-medical applications, such as single molecule sensing and DNA sequencing.

Wavelength-Independent Directional Couplers for Integrated Silicon Photonics

It has been shown that the wavelength-dependent performance of a directional coupler (DC) in silicon-on-insulator (SOI) platform can be greatly engineered by suitable design optimizations. Semianalytical coupled mode theory is used to optimize a nearly wavelength-independent design of a DC in an SOI substrate with a device layer thickness of 220 nm, operating in TE-polarization ( $\lambda \sim$ 1550 nm). The transmission characteristics of fabricated DCs are found to be indeed wavelength independent over a bandwidth of ${\text{100 nm}}$ (1525 nm $\leq \lambda \leq$ 1625 nm), consistent with the theoretical predictions. The average excess loss of such directional couplers is evaluated as $\sim\text{0.8}$ dB and there are scopes for its further reduction. These DCs are then used further to demonstrate integrated optical building blocks like power splitters (2 $\times$ 2, 1 $\times$ 4), Mach–Zehnder interferometers (2 $\times$ 2), and all-pass microring resonators. Their performances are also found to be uniform within the wavelength range mentioned and, thus, making them suitable for integrated silicon photonics for broadband applications.

RF Performance of &lt;italic&gt;In Situ&lt;/italic&gt; SiN&lt;italic&gt;x&lt;/italic&gt;Gate Dielectric AlGaN/GaN MISHEMT on 6-in Silicon-on-Insulator Substrate

A high power-added efficiency and low dynamic on-resistance ( $R_{ \mathrm{\scriptscriptstyle ON}})$ AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistor (MISHEMT) with in situ SiN x insulator design was demonstrated on 150-mm silicon-on-insulator (SOI) substrate. Compared to traditional high-resistivity Si substrate, SiN x /AlGaN/GaN MISHEMT grown on the SOI 5- $\mu \text{m}$ -thick Si active layer performed better tensile stress relaxation and surface flatness. Based on Hall measurement results, electron mobility and the sheet charge density on SOI substrate were improved simultaneously owing to a lower-defect density which is also proofed by pulse measurement and low-frequency noise measurement. Due to the low-feedback substrate capacitance, the bandwidth, and the linearity were also improved simultaneously by SOI substrate design.

Fabrication of Phosphor-Free III-Nitride Nanowire Light-Emitting Diodes on Metal Substrates for Flexible Photonics

In this paper, we report our study on high-performance III-nitride nanowire light-emitting diodes (LEDs) on copper (Cu) substrates via the substrate-transfer process. Nanowire LED structures were first grown on silicon-on-insulator (SOI) substrates by molecular beam epitaxy. Subsequently, the SOI substrate was removed by combining dry- and wet-etching processes. Compared to conventional nanowire LEDs on Si, the nanowire LEDs on Cu exhibit several advantages, including more efficient thermal management and enhanced light-extraction efficiency (LEE) because of the usage of metal reflectors and highly thermally conductive metal substrates. The LED on Cu, therefore, has stronger photoluminescence, electroluminescence intensities, and better current–voltage characteristics compared to the conventional nanowire LED on Si. Our simulation results further confirm the improved device performance of LEDs on Cu, compared to LEDs on Si. The LEE of the nanowire LED on Cu is nine times higher than that of the LED on Si at the same nanowire radius of 60 nm and spacing of 130 nm. Moreover, by engineering the device-active region, we achieved high-brightness phosphor-free LEDs on Cu with highly stable white-light emission and high color-rendering index of ∼95, showing their promising applications in general lighting, flexible displays, and wearable applications.

Comparative Study of RESURF Si/SiC LDMOSFETs for High-Temperature Applications Using TCAD Modeling

This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300 °C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an off-state leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariablewith substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectanglepower pulse setup in TechnologyComputer-Aided Design simulations.

GaN Devices on a 200 mm Si Platform Targeting Heterogeneous Integration

GaN-based high electron mobility transistors (HEMTs) were fabricated on 200-mm silicon-on-insulator (SOI) substrates possessing multiple crystal orientations. These SOI substrates have the Si (100)-SiO2-Si (111) structure, which allows Si (111) to be exposed below the buried oxide to enable GaN epitaxial growth adjacent to Si (100). The current collapse in GaN HEMTs of $ patterns is 2%–6%, which is remarkably lower than the devices on blanket materials. We believe that stress relaxation resulting from substrate patterning contributes to the reduction of current collapse. By creating small GaN patterns on a larger diameter Si wafer, co-integration of GaN with Si technology may be possible.

Compact On-Wafer Test Structures for Device RF Characterization

The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50- $\mu \text{m}$ -pitch RF probes. It is shown that by using these new test structures, the layoutgeometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100– $150~\mu \text{m}$ -pitch RF probes. 50- $\mu \text{m}$ -pitch de-embedding structures have been implemented on 0.18- $\mu \text{m}$ RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions.

Integration of solid-state nanopores into a functional device designed for electrical and optical cross-monitoring.

We present a new strategy for fabricating a silicon nanopore device allowing straightforward fluidic integration and electrical as well as optical monitoring. The device presents nanopores of diameters 10nm to 160nm, and could therefore be used to obtain solvent-free free-standing lipid bilayers from small unilamellar vesicles (SUV) or large unilamellar vesicles (LUV). The silicon chip fabrication process only requires front side processing of a silicon-on-insulator (SOI) substrate. A polydimethylsiloxane (PDMS) microfluidic interface is assembled on the silicon chip for fluidic handling and electrical addressing. We detail the electrical specifications of our device and some perspectives showing that the use of an SOI substrate is a convenient way to reduce the electrical noise in a silicon nanopore device without the need of a photolitographic patterned passivation layer. We then demonstrate simultaneous electrical and optical monitoring by capturing negatively charged fluorescent nanoparticles. Finally, in the perspective of solvent-free free-standing lipid bilayers, we show that incubation of SUV results in a drastic increase of the device electrical resistance, which is likely due to the formation of a free-standing lipid bilayer sealing the nanopores. Graphical abstract ᅟ.