Silicon-on-insulator MOSFETs Research Articles

Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process.

This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns) for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling. This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity. The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105 V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4 % to the drain side, which obtained a value of -0.04 eV at the terminal end. This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

Two-dimensional analytical model for fully depleted SOI MOSFETs with vertical trapezoid doping including effects of the interface trapped charges

The two-dimensional (2D) potential distribution for vertical trapezoidal doping thin-body fully depleted (FD) silicon-on-insulator (SOI) devices is derived by adopting the evanescent mode analysis method, in which the 2D effects in gate oxide region, channel region and buried oxide region are taken into account. Moreover, the effects of interface trapped charge are considered. Using this potential model, the subthreshold performance of the device including subthreshold current, and subthreshold swing under various conditions have been studied. The result shows that the analytical model is good agreement with the simulated results. Therefore, it provides a feasible way of developing new 2D models for vertical trapezoidal doping thin-body FD SOI devices. Besides offering the physical insight into device physics, the analytical model provides the basic designing guidance for vertical trapezoidal doping thin-body FD SOI devices.

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.

Analytical workload dependence of self-heating effect for SOI MOSFETs considering two-stage heating process

Dynamic self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFET is comprehensively evaluated by ultrafast pulsed I–V measurement in this work. It is found for the first time that the SHE complete heating response and cooling response of SOI MOSFETs are conjugated, with two-stage curves shown. We establish the effective thermal transient response model with stage superposition corresponding to the heating process. The systematic study of SHE dependence on workload shows that frequency and duty cycle have more significant effect on SHE in first-stage heating process than in the second stage. In the first-stage heating process, the peak lattice temperature and current oscillation amplitude decrease by more than 25 K and 4% with frequency increasing to 10 MHz, and when duty cycle is reduced to 25%, the peak lattice temperature drops to 306 K and current oscillation amplitude decreases to 0.77%. Finally, the investigation of two-stage (heating and cooling) process provides a guideline for the unified optimization of dynamic SHE in terms of workload. As the operating frequency is raised to GHz, the peak temperature depends on duty cycle, and self-heating oscillation is completely suppressed.

Investigation on boron diffusion effects in buried oxide of Si nanocrystals (Si NCs) embedded Silicon-on-Insulator

Si nanocrystals (Si NCs) embedded in an oxide matrix can introduce additional defects and stress, which enhances the dopant diffusion and trapping in buried oxide (BOX) layer that can be detrimental for device applications. In this paper, we have investigated the boron gettering effect of Si NCs in Silicon-on-Insulator (SOI) using Secondary Ion Mass Spectrometry (SIMS), Transmission Electron Microscopy (TEM). And image identification technique is used to analysis the Si NCs concentration in BOX. By analyzing the decline of threshold voltage and vanishing of kink effect of nMOSFET with different Si NCs concentration, it is found that the variation of boron concentration is induced by Si NCs. The higher annealing temperature and boron concentration in top Si can accelerate the boron diffusion velocity. The boron concentration rises almost tenfold in BOX layer when Si implantation dose increases from 5 × 1015 cm−2 to 5 × 1016 cm−2. The results indicate that the boron gettering effect is caused by Si NCs and highly related to the Si NCs induced defects and stress. This paper may offer a guidance for compensating the boron loss in SOI MOSFET fabricating process.

Investigation of Transient Two-Stage Thermal Equivalent RC Network of SOI-MOSFETs Using Nano Double-Pulse Measurement

The self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFETs brings challenges to the measurement and modeling of transient electrothermal characteristics. For the first time, this study obtains the transient two-stage thermal equivalent RC network of SOI MOSFETs by nano double-pulse measurement combined with network identification by a deconvolution (NID) method. The two-stage model provides a comprehensive reference for the accumulation of residual heat under dynamic operation. We reveal that since the oxide layer acts as a thermal reservoir, the heat dissipation process can be divided into three phases according to thermal time constants. The results of geometry dependence of thermal parameters show that the gate length and width-to-length ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}/{L}$ </tex-math></inline-formula> ) increase: the thermal resistance trend of both stages decreases, the one-stage thermal time constant increases, but the two-stage thermal time constant decreases. Also, as the scaling of device dimension and mutual thermal coupling, the thermal transient response boosts significantly.

Gate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETs

Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>. Thus, thermal time constants of &#x007E;760 ns, extracted from a variety of gate lengths, are correctly predicted.

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range. The high frequency performances of FD SOI transistors are presented at room but also at cryogenic and high temperature. Recently published results for FD SOI switches and low noise amplifiers are summarized. And finally, the potential interest and challenges to move from standard to high resistivity FD SOI substrates are discussed.

Origin of the Out-of-Equilibrium Body Potential In Silicon on Insulator Devices With Metal Contacts

This work addresses the origin of the transient body potential variation in silicon on insulator (SOI) with deposited metal contacts, under back-gate bias sweep from accumulation to inversion. The phenomenon arises from the difficulty to inject carriers into the silicon film due to the Schottky contact between the metal and the low p-type doped silicon. The Schottky diode current is controlled by the back-gate voltage, which fixes the potential at the bottom of the low-doped film. When the back-gate voltage drives the silicon film towards inversion, the limited current from the Schottky contact induces a deficit of minority carriers in the film and brings the body potential in an out-of-equilibrium regime. This phenomenon will be reproduced with numerical modelling based on Poisson and continuity equations, including the quasi-Fermi potential. The transient character and its dependence on the Schottky barrier height will be evidenced. A simple and effective combination of the classic Schottky current equation and inversion current calculated from the Lambert function, as in fully depleted (FD)-SOI MOSFETs, confirms the origin of the effect.

Controlling of Floating-Body and Thermal Conductivity in Short Channel SOI MOSFET at 30 nm Channel Node

Ultra low-power Silicon-on-Insulator (SOI) transistor makes it possible to lower the supply voltage and reduce the power dissipation. However, these SOI MOSFET are still suffering from short channel effects (SCEs), the floating body effect (FBE) and self-heating effects (SHEs). In order to attenuate these problems, a new structure has been introduced and analyzed in this paper. The leakage current is minimized by using wide band gap material (GaP) and modifying buried oxide layer (SiO2-Si3N4-SiO2) in 30 nm channel node SOI MOSFET. The high thermal conductivity HfO2 and Si3N4 material being applied in the mentioned structure that helps to reduce the maximum temperature and controls self-heating effects. Also, the extra floated holes in the active region is reduced by a new N+-P+ diode created at the interface of the N+ source region and P+ silicon layer resulting in control FBE. The other important parameters like SS, gm, Ion/Ioff ratio, Vth, DIBL of an SOI MOSFET are studied to increase reliability of the device. The experimental data and the proposed SOI structure are simulated by using device simulator sentaurus TCAD for analysis purpose. The analyzed results of this work are useful for device optimization in future prospect. Extracted numerical outcomes make an evidence to replace conventional SOI by the modified structure.

Boosting the MOSFETs Matching by Using Diamond Layout Style

This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.

Charge-Based Continuous Equations for the Transconductance and Output Conductance of Graded-Channel SOI MOSFET’s

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement in a wide range of bias.

Deep-Depletion Effect in SOI Substrates and its Application in Photodetectors With Tunable Responsivity and Detection Range

We present an interesting transient effect found in silicon-on-insulator (SOI) transistors, where the drain current responds slowly to a back-gate voltage ( ${V}_{\text {BG}}$ ) pulse. This transient mechanism is due to the deep-depletion region in the SOI substrate induced by the ${V}_{\text {BG}}$ pulse and has been validated by experimental and TCAD simulation results. The deep-depletion characteristic can be employed for photodetection in a fully depleted (FD)-SOI MOSFET device. We have measured the photoresponse of the FD-SOI MOSFET under various light illumination conditions and studied systematically the impact of the ${V}_{\text {BG}}$ pulse duty ratio, amplitude, and period on the responsivity and detection range. An optimized device structure, fabricated in an advanced ultrathin body and buried oxide (BOX) (UTBB) SOI technology, shows low operation voltage and extended detection range.

Improvement of a Nano-scale Silicon on Insulator Field Effect Transistor Performance using Electrode, Doping and Buried Oxide Engineering

In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a silicon region has embedded in the buried oxide. In order to reduce the device leakage current and controlling the threshold voltage, a p-type retrograde doping is introduced into channel region. Since the air has the least permittivity among materials, it can be utilized to decrease the device parasitic capacitances. Based on this, an air gap is embedded in the buried oxide near the silicon to improve RF performance of the device. Because the source and drain electrodes are embedded in and over the silicon film in the source and drain regions, we called this structure EEIOS-SOI MOSFET. “EEIOS” stands for “Embedded Electrodes In and Over the Silicon film”. During this work, EEIOS-SOI MOSFET is compared with a conventional SOI MOSFET and another SOI MOSFET with just Embedded Electrodes In the Silicon Film (EEIS-SOI). EEIS-SOI presents better electrical figure of merits including lower subthreshold slope and lower leakage current in simulations. An immense investigation among these devices shows that EEIOS-SOI MOSFET has better transconductance, lower gate injection leakage current and lower temperature related to DC parameters and higher cut off frequency, gain bandwidth product and unilateral power gain related to AC figures of merits compared to its counterparts.

Total ionization dose effects and compensation in a counting type double SOI pixel sensor

We are developing the monolithic pixel sensors based on a 0.2 μm fully-depleted Silicon-on-Insulator (SOI) technology. One of the major issues in the SOI device is the total ionization dose (TID) effects in high-radiation environment. We studied the TID effects on a fully functional counting type pixel sensor based on Double SOI process. The device was irradiated to different dose at different region, by an X-ray tube operated at 30 kV with copper target. The degradation of the SOI MOSFET characteristics and the pixel response have been studied. The SPICE simulations using the transistor model with TID dose were performed on the pixel amplifier-shaper-discriminator (ASD) circuit to understand the malfunction in circuit level. In double SOI sensor, the SOI2 layer could compensate the positive charge induced by TID in buried oxide (BOX) layer when negatively biased. Such a compensation effectiveness has been observed in a counting type pixel sensor CPIXTEG3b.

Self-Heating in 40 nm SOI MOSFETs on High Resistivity, Trap-Rich Substrates

Closely spaced n-channel MOSFETs have been used to compare the self-heating in nominally identical devices fabricated on conventional and high resistivity, trap-rich silicon-on-insulator (SOI) substrates. One of the MOSFETs operates above threshold and in saturation to heat the active silicon, while the other is biased into the sub-threshold regime and operates as a local thermometer. The trap-rich layer in the high resistivity substrates consists of a highly defected, poly-Si layer just below the buried oxide. Grain boundaries in the poly-Si lead to increased phonon scattering compared to single crystal silicon, with a corresponding decrease in thermal conductivity. Despite the reduced thermal conductivity there appears to be no difference in the self-heating between the MOSFETs on the high resistivity, trap-rich substrates compared to those on the conventional low resistivity substrates.

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

AbstractThe semiconductor industry has implemented the technique of wrapping the gate electrode on different sides of channel to mitigate the degrading electrostatic effects in nanometer transistor. Intel adopted trigate architecture, wherein the channel is surrounded by gate electrode on three sides to improve the gate control over the channel. In order to further enhance the performance and diminish the short channel effects, triple material trigate silicon‐on‐insulator (SOI) MOSFET is explored in this work. An analytical model to determine the device electrostatics and match deviations due to device geometry has also been developed. The consequence of quantum confinement effects (QMEs), which arise due to ultra‐thin body structure, on the inversion charge and threshold voltage has also been included. Thus, the analytical model presented in this work is based on a self‐consistent solution of three‐dimensional Poisson's equation and two‐dimensional Schrodinger equation with proper boundary conditions. The model is verified by the uniformity obtained between the results from analytical model and TCAD simulations. The superiority of the device has been demonstrated by comparing performance parameters like potential distribution, field variations, drain induced barrier lowering (DIBL) with already existing device structures like single material trigate (SMTG) and dual material trigate (DMTG) SOI MOSFETs

Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFETs Using Substrate Bias Induced Effects

This paper proposes the substrate bias voltage dependent subthreshold models of channel potential, threshold voltage, current, drain induced barrier lowering, and subthreshold swing for tri-gate silicon-on-insulator (SOI) MOSFET s (TG- MOSFET s). The substrate induced surface potential effect has also been included in the derived models. A quasi-three-dimensional (3-D) approach has been used to derive the minimum of channel potential, which is later used to derive models of threshold voltage, current, drain induced barrier lowering, and swing. The analytical results of TG-SOI MOSFET have been compared with the simulation results obtained from the Visual TCAD, a 3-D device simulator from Cogenda Pvt. Ltd.

Compact Model for Tunnel Diode Body Contact SOI n-MOSFETs

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools.

Investigation of Geometry Dependence of Thermal Resistance and Capacitance in RF SOI MOSFETs

According to the thermal theory, the self-heating effect is equivalent to an R–C thermal equivalent circuit. Based on a small-signal equivalent circuit analysis, an analytical method to extract the thermal resistance and capacitance for RF silicon-on-insulator (SOI) MOSFETs is proposed in this paper. The geometry dependence of the thermal resistance and capacitance is investigated by using this method. The method is verified by using RF partial depletion-SOI process. The results show that the thermal resistance decreases and the thermal capacitance increases as the effective channel area increases. A simple equation to estimate the thermal characteristics is proposed to help optimize the device structure and circuit design for application. This method is easy to scale and adjust to devices with different dimensions and fabrication processes.