Self-Heating in 40 nm SOI MOSFETs on High Resistivity, Trap-Rich Substrates

Abstract

Closely spaced n-channel MOSFETs have been used to compare the self-heating in nominally identical devices fabricated on conventional and high resistivity, trap-rich silicon-on-insulator (SOI) substrates. One of the MOSFETs operates above threshold and in saturation to heat the active silicon, while the other is biased into the sub-threshold regime and operates as a local thermometer. The trap-rich layer in the high resistivity substrates consists of a highly defected, poly-Si layer just below the buried oxide. Grain boundaries in the poly-Si lead to increased phonon scattering compared to single crystal silicon, with a corresponding decrease in thermal conductivity. Despite the reduced thermal conductivity there appears to be no difference in the self-heating between the MOSFETs on the high resistivity, trap-rich substrates compared to those on the conventional low resistivity substrates.