SOI FinFETs Research Articles

IMPACT OF SOURCE (DRAIN) DOPING PROFILES AND CHANNEL DOPING LEVEL ON SELF-HEATING EFFECT IN FinFET

In this work the impact of the doping profile in the source and drain areas on the self-heating effect in SOI FinFET is simulated at different doping levels in the channel. Constant profile as well as two types of analytical profiles are considered. The impact of the doping profile on the threshold voltage and on the ratio Ion/Ioff at different doping levels of the channel is also considered. To consider the self-heating effect the thermodynamic transport model in TCAD Sentaurus software is used for simulation. The results of simulation show that self-heating effect, threshold voltage, and Ion/Ioff ratio considerably depend on the doping profile in source and drain areas.

Degradation Induced by Total Ionizing Dose and Hot Carrier Injection in SOI FinFET Devices.

The working environment of electronic devices in the aerospace field is harsh. In order to ensure the reliable application of the SOI FinFET, the total ionizing dose (TID) and hot carrier injecting (HCI) reliability of an SOI FinFET were investigated in this study. First, the influence of TID on the device was simulated. The results show that TID causes the threshold voltage to decrease and the off-state current and subthreshold swing to increase. TID causes more damage to the device at high temperature and also reduces the saturation drain current of the device. HCI causes the device threshold voltage to increase and the saturation drain current to decrease. The HCI is more severe at high temperatures. Finally, the coupling effects of the two were simulated, and the results show that the two effects cancel each other out, and the degradation of various electrical characteristic parameters is different under different coupling modes.

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (ION), drain current (IDS), transconductance (gm), energy bands, lower subthreshold swing (SS), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

A breakthrough for temperature and linearity stability from device to circuit-level with 14 nm junctionless SOI FinFET: Advancing K-band LNA performance

SOI junctionless (JL) FinFETs are well-suited for future wireless communication systems; however, they suffer from the self-heating effect (SHE), which diminishes performance at higher temperatures. We proposed a novel structure called p-layer JL-FinFET (pL-JL-FinFET) to improve high-frequency performance at high temperatures. The Ge p-layer beneath the Silicon Fin increases electron current density and enhances device performance. Two high thermal conductivity 4H-SiC boxes are placed below the source and drain regions to overcome SHE. The pL-JL-FinFET exhibits the maximum transconductance of 148 μS, unity gain cut-off frequency of 455 GHz, and maximum available gain of 28.6 dB, which are improved by 208 %, 26 %, and 35 %, respectively, compared to regular JL-FinFET. Temperature analysis demonstrates suppressed SHE and better thermal stability than the regular JL-FinFET. Also, the pL-JL-FinFET shows superior thermal behavior in different fin shapes. The pL-JL-FinFET with a rectangular fin shape shows excellent linearity and high-frequency performance, achieving unconditional stability and minimum noise figure (NFmin) of less than 1 dB. An extracted small signal model is used to design a K-band low noise amplifier (LNA) with maximum NF and gain values of 0.75 dB and 18.7 dB. The pL-JL-FinFET opens opportunities for reliable, high-performance RF circuits while effectively managing thermal behavior.

Single event transient of SOI FinFET with total ionizing dose irradiation

Total ionizing dose (TID) irradiation impacts the device leakage currents or threshold voltage, which affects the single event transient (SET) vulnerability of electronics under radiation environment. SET response of SOI FinFET at 14 nm technology node after TID exposure is carried out at different dose level. Results show that the drain current peak presents a slight fluctuant with total dose, while the collected charge and the bipolar amplification coefficient first decrease with total dose and then increase. The potential reason is also discussed from competing mechanisms associated with decreasing threshold voltage from TID irradiation and increasing the drain diffuse current from the potential of the channel.

Modelling of FinFET based ON bipolar cell of silicon retina

—In this paper, we proposed a SOI FinFET based ON bipolar cell of silicon retina which plays an important role in neuromorphic applications like differential motion detection. Low power consumption along with biological plausibility is one of the crucial parameters of any neuromorphic retinal circuit as in the brain all biological systems consisting of billions of neurons consume power in terms of a few μwatts. First, the output of linkage cell between inner and outer plexiform layer i.e. bipolar cell is reconstructed and verified using developed ionic current based mathematical model which is established considering Hodgkin-Huxley model as the base model, and then biological behavior of the ON bipolar cell is mimicked through circuit using 180 nm, 90 nm and 45 nm Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The power consumption in each case is obtained to be approximately 18.5 nW, 10.5 nW and 1 nW which is much larger than the power consumed by biological bipolar cell. Moreover, the same circuit is implemented with 32 nm Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) device. It is observed that SOI FinFET based ON bipolar cell consumes 17.5 pW power which is less in comparison to MOSFET based bipolar cell. The output of bipolar cell is matched with biological nature of the waveform in each case.

SOI FinFET Design Optimization for Radiation Hardening and Performance Enhancement

This work proposes Total Ionizing Dose (TID) hardening techniques compatible with conventional 14-nm-node silicon-on-insulator (SOI) FinFETsf process flows through performing 3-dimensional (3-D) simulations based on technology computer-aided design (TCAD) tools. The simulation results reveal a significantly critical TID impact induced by trapped charges in the buried oxide (BOX) and the spacer with calibration against 14 nm SOI FinFETfs experimental data (error < 6%). Inspired by the physical interpretation, an optimization technique featuring an optimized gate structure, spacer length, and substrate bias is designed. The optimized gate structure is utilized to enhance the local gate-to-channel coupling at the bottom and reduce the generation and capture of electron-hole pairs. By reducing the spacer length, a lower sensitive volume in the spacer can effectively suppress the TID response. The setting of the negative substrate bias greatly improves the subthreshold characteristics, weakening the TID effect in the BOX. By adopting the combined optimization including these techniques, the threshold voltage shift (VTH) induced by a 5 Mrad(SiO2) irradiation can be reduced to 21 mV, whereas VTH is 45 mV with only gate structure optimized and 97 mV without hardening. Meanwhile, the ION/IOFF after radiation increases to 1 × 107, which is at least four orders of magnitude better than the original device. Meanwhile, subthreshold swing (SS) is reduced from 81 mV/dec to 71 mV/dec, and Drain Induced Barrier Lowering (DIBL) is reduced from 120 mV/V to 99 mV/V, respectively. The combined optimization design is demonstrated as an effective method to improve the tolerance against TID irradiation without compromising performance, promoting 14 nm SOI FinFET’s application in future harsh space environments.

Numerical Investigation of the Electrothermal Properties of SOI FinFET Transistor

This paper investigates the non-Fourier transient heat transfer in an SOI FinFET transistor. The calibrated drift-diffusion (D-D) model in conjunction with the ballistic diffusive (BDE) model is used as an electrothermal model to predict phonon and electron transports in the quasi-ballistic regime. The finite element method has been employed to generate the numerical results. The proposed mathematical formulation was found to capture the transfer characteristics and the temporal temperature as given by TCAD simulation and experimental data. On the other hand, we have demonstrated that after 100 ns, the 14 nm Bulk FinFET supports better temperature distribution than the 14 nm SOI FinFET.

Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

The impact of spacer on the single event response of SOI FinFET at 14 nm technology node is investigated. Based on the device TCAD model, well-calibrated by the experimental data, it is found that the spacer presents the enhancement on single event transient (SET) compared with no spacer configuration. For single spacer configuration, due to enhanced gate control capability and fringing field, the increments in SET current peak and collected charge for HfO2 are the least with 2.21%, 0.97%, respectively. Four possible dual ferroelectric spacer configurations are proposed. The placement of ferroelectric spacer at S side and HfO2 spacer at D side brings to weaken SET with the variation in current peak and collected charge by 6.93%, 1.86%, respectively. The reason may be its enhanced gate controllability over the S/D extension region, which improves the driven current. With linear energy transfer increasing, SET current peak and collected charge present the trend of increase while the bipolar amplification coefficient reduces.

Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET.

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications.

FinFET based photoreceptor for silicon retina to reduce power consumption

In this paper, we propose a SOI FinFET device based photoreceptor for silicon retina to reduce power consumption. Nowadays, in the field of neuromorphic engineering the main aim of the researcher is to implement a biological nervous system based on silicon devices. Major performance metrics which influence the design of neuromorphic circuits along with biological plausibility are compactness, low power consumption, scalability and computational complexity. Moreover, to process the information biologically billions of neurons consume only a few watts of power. However, present design of silicon photoreceptor consumes power much larger than actual biological photoreceptor. Hence to achieve low power consumption we are using nanometer SOI FinFET device technology. In this paper, output of the outer retinal cell, namely photoreceptors, is reconstructed and verified with the help of developed ionic current based mathematical model of the retina. The model contains non-linear differential equations based on the fundamental framework of the Hodgkin-Huxley model. In order to closely match the biological response, the selection of parameters of membrane voltage and other membrane dependencies through compartments are done using MATLAB simulation. After mathematical verification, the biological behavior of photoreceptor cell of retinal system is mimicked through circuit using 180 nm Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and 32 nm Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) device. It is observed that SOI FinFET based photoreceptor for silicon retina circuit consumes less power in picowatts matching the power consumption of biological retinal system, as compared with MOSFET based circuits.

RF and Linearity Analysis of Heterojunction-free Ga2O3 FINFET with Respect to Different Fin Widths and Temperatures

In this paper we have proposed a Heterojunction free Ga2O3 FinFET, and the different electrical characteristics have been analysed. Fin width is one of the most important parameters for the device performance, hence all the electrical charaterstics have been analysed for different fin widths. Temperature is one of the most important considerations for high power applications and hence electrical characteristics have been analysed by varying temperature also. Here, in the work done an exhaustive study on the RF and Linearity analysis on Heterojunction-free Ga2O3 layer FINFET using TCAD device simulator is demonstrated. The impact when varying the widths of fin along with the temperature variation for the device on various RF parameters like Drain current, gm (Transconductance), gd (output Conductance), Cgs and Cgd (gate capacitances), fT (cut-off frequency) are studied. The same has been performed even to calculate different linearity parameters such as gm2, gm3, VIP3, IIP3, IMD3, 1db compression point. It’s observed that to have high value for fin width and to have lower temperature value is much worthier for RFIC applications. In order to exhibit the superiority of the Ga2O3 FINFET it has been compared with the SOI FINFET.

Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET

Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET

Study on Single Event Transient Pulse Characteristics of 16nm SOI FinFET Devices

In this paper, the single event transient (SET) characteristics of the advanced 16 nm SOI FinFET device are investigated. The impacts of five different variables on the SET response of the 16 nm SOI FinFET device are investigated, including the incident position, particle LET value, particle characteristic radius, incident angle, and drain bias. It is found that 1) unlike traditional planar devices, the SET shape of the 16 nm SOI FinFET device changes significantly. The “SET tail” caused by charge diffusion disappears, the SET time width is at the magnitude of tens of ps, and the total collected charge is at the magnitude of fC. 2) The most sensitive region of SET is the center of the gate. Under the condition that the incident position is the center of the gate, the amount of collected charge is 1.33 times that of the center of the drain. 3) Under the premise of the same LET value, the larger the radius of the particle, the smaller the SET amplitude generated, due to the entire electron-hole pairs participating in the SET response with a smaller radius. 4) The larger the incident angle of the particle, the smaller the SET amplitude generated by the FinFET device. When the incident angle is 45°, the amount of charge collected at the drain is only 0.23 times that of the normal incidence. 5) Changing the drain bias of the device results in a nearly constant SET curve, which is one of the features that distinguishes the FDSOI device from other devices.

Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)

This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific devices. An SOI FinFET device consists of three independent gates. By connecting the various gates, multiple working modes are obtained. Compared with traditional FinFETs, the multi-enhanced operation gate fin field-effect transistor in this study combines independent gates by connecting the selection modes; thus, a possible operation can be performed to attain a FinFET with five equivalent working states in only one device. This novel function can enable the device to work with multiple specific voltages and currents by connecting the corresponding gate combinations, augmenting the integrated degrees and shifting the working modes, thereby meeting the different needs of high-speed, low-power, and other potential applications. Further, the potential applications are highlighted.

Analysis of location and LET dependence of single event transient in 14 nm SOI FinFET

FinFET, with narrow silicon fin, and high k/metal gate stacked combined with SOI technology brings benefits to radiation effects. Single event transient (SET) of SOI FinFET at 14 nm technology node is simulated by TCAD. The device model is calibrated by the experiment data. The effects of ion strike locations and linear energy transfer (LET) on SET are analyzed. The trends of the transient current peak, the collected charge, the deposited charge and the bipolar amplification are discussed. The results indicate that the most sensitive area of FinFET to SET is the gate-drain junction of fin. With LET increasing, the transient current peak and the collected charge increase while the bipolar amplification decreases.

Investigation of Single Event Transient Induced by Process Variability in 14 nm High-k/Metal Gate SOI FinFET Devices

Investigation of Single Event Transient Induced by Process Variability in 14 nm High-k/Metal Gate SOI FinFET Devices

Numerical investigation and temperature-based analysis of the analog performance of fully gate-covered junctionless FinFET

This work presents a temperature-based investigation of the analog performance parameters of a fully gate-covered junctionless SOI FinFET, which excludes source and drain extensions. The device is studied at 20/40 nm nodes with high-k gate oxide. The design provides a higher ON-current and better short channel characteristics (<70 mV/dec SS, around 30 mV/V DIBL) with an excellent switching ratio (100x better than conventional device). The temperature investigation reveals robust device integrity at higher temperatures. The short channel parameters degrade more rapidly for the conventional device with an increase in temperature as compared to fully gate-covered devices. At 600 K, the difference of DIBL was more than 25% between the conventional and proposed devices, the SS of the device increased by about 16.67%, and the switching ratio was better by an order of magnitude. This shows that the device is a potential candidate for applications where temperature resilience is of utmost importance.

Estimating the performance of SOI FinFET transistor using electro-thermal formulation in conjunction with the quasi-ballistic effective electron mobility approach

Modeling and simulating FinFET based circuits, disentangled as Physics-based FinFET models, constitute predictive technology models for device and circuit simulations. The electrostatic properties as well as the electron and phonon transport are very responsive to the thermal effects in diffusive as well as in quasi-ballistic regimes suggesting thereby, the necessity of their consideration for effective device modeling and design particularly in nano FinFET devices. In this paper, we describe the calibration of the drift-diffusion (D-D) transport approach for simulating the quasi-ballistic effect in short channel occurring in nanoscale devices. A strong coupling of the calibrated D-D model with the enhanced Ballistic-Diffusive Equation (BDE), susceptive to prescribe the phonon and electron transports is introduced. The Finite Element Method (FEM) is used to produce results by numerical simulation of the electro-thermal model offered in Bulk and SOI FinFET devices. We have found that the proposed mobility model performs quite well and mainly infuences the drain current and the heat source by Joule effect. Our results extracted from the calibrated D-D model are compared and contrasted with those obtained experimentally and with those obtained with the numerically exact configuration. A decent agreement between the proposed model dealing with SOI FinFET as well as Bulk FinFET and the experimental data is obtained. Results obtained by using the enhanced electro-thermal model hold promise for thermal simulations of heat transport in Bulk and SOI FinFET devices, suggesting that the dopant concentration have a crucial role for the increasing of the temperature inside the Bulk/SOI FinFET.