Silicon-on-diamond Research Articles

A Capacitance Model for Front- and Back-Gate Threshold Voltage Computation of Ultra-Thin-Body and BOX Double-Insulating Silicon-on-Diamond MOSFET

In this paper, a capacitance model for near threshold voltage computation of Ultra-Thin-Body and BOX (UTBB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is proposed. The transistor has a second insulating layer on top of the first insulating layer of a conventional SOD MOSFET which partially covers the diamond layer. The device’s simulation results of the front- and back-gate threshold voltages and the computed model’s threshold voltages - in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses - are compared. In addition, length of the source/drain overlap with the second insulating layer is varied and the device simulation results are compared with those of the model findings. Results of the aforesaid comparison are found to be promising; more than 20 mV change in front-gate threshold voltage is observed at the range of 5 nm to 43 nm. Moreover, the model is found to be applicable in computations of front- and back-gate threshold voltage of 22 nm DI UTBB SOD MOSFET for low drain voltages. Finally, the model’s physical findings present insight on the device’s parameters that directly influence the threshold voltage

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (∼3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Investigation and Comparison of the DIBL Parameter and Thermal Effects of SOD Transistors and SOI Transistors and Improving Them with the Change of Their BOX Thicknesses

In this paper, thermal effects and Drain Induced barrier lowering (DIBL) of silicon-on-insulator (SOI) and silicon-on-diamond (SOD) transistors with 22 nm channel lengths using hydrodynamic simulations have been investigated. Thermal conductivity of diamond in contrast to thermal conductivity of silicon dioxide is significantly higher. Hence, the heat transfers faster in silicon-on-diamond transistors. Lattice temperature of SODs is lower than that of similar SOIs. By using SODs in Integrated circuits with the first transistor turning on and active, neighboring transistors will have the same level of heat as the active transistor. As a result, the DIBL factor will be increased; this is an undesired phenomenon in CMOS applications. To resolve this issue, we propose a new method which is the thickness reduction of buried diamond layers inside of transistors. Due to this change, DIBL of active transistor will be improved, the exceeding lattice heat of side transistors will be evacuated through the devices and their temperatures will be deduced in large scale.

Impact of three-dimensional stacking silicon on diamond substrate for the electrostatic discharge protection device

In this paper, the electrostatic-discharge (ESD) protection capabilities of the protection devices fabricated on a silicon-on-diamond (SOD) structure and a conventional Si substrate are compared. The results showed that the ESD protection capability of the SOD substrate is higher than that of the silicon-on-insulator (SOI) substrate. We also evaluate the ESD protection device suitable for the SOD structure. In addition, we propose the three-dimensional (3D) stacking structure suitable for a power supply on a chip (power-SoC) and the best location for the implementation of the ESD protection device based on the results of device simulations.

Impact of the silicon on diamond structure for high temperature switching applications

This paper reports comparisons of silicon-on-diamond (SOD) structure to the conventional silicon-on-insulator (SOI) for high temperature switching applications. For high temperature applications (>473 K), major loss is caused by on-resistance and leakage current. Shrinking the channel length increases loss at 573 K. The power MOSFETs fabricated on SOD substrate shows lower loss compared with that fabricated on the conventional SOI substrate because the SOD can suppress the self heating effect.

A novel structure to improve DIBL in fully-depleted silicon-on-diamond substrate

In this paper, a novel silicon-on-diamond (SOD) MOSFET structure is proposed. The new structure eliminates the degraded drain induced barrier lowering (DIBL) inherently observed in SOD devices. A second insulating layer over the buried diamond layer is integrated which partially covers the diamond layer. An expression for the total body capacitance through the insulating layers is obtained. Using analytical model, the second insulating layer dimensions are computed. In order to evaluate the impact of second insulating layer on the device characteristics, hydrodynamic numeric analysis is performed. Device simulation results verified the analytical model in DIBL improvement. Maximum lattice temperature of the new structure is well below SOI device and 5% higher in comparison with SOD substrate. The device simulation results demonstrate short channel effects improvement and suppressed self-heating effects.

Electrical properties of laser-bonded Silicon-On-Diamond samples

In this work we report preliminary tests aimed at the implementation of a Silicon-On-Diamond (SOD) radiation sensor. SOD materials have been prepared by continuously scanning a 20ps pulsed 355nm laser beam on the silicon–diamond interface. A pixel monolithic sensor has also been bonded to diamond with the same technique and tested to show that a complex electronic chip can undergo the process without any damage. Through silicon vias have been fabricated by laser drilling on the silicon side of the SOD samples and their insulation from the silicon bulk has been tested. The charge collection efficiency of a diamond sensor with laser-written graphitic contacts has been measured, to demonstrate a reliable and simple way to fabricate ohmic contacts on the diamond side of the SOD devices. Finally, a SOD material with electric contacts on the silicon and on the diamond sides has been tested as a particle sensor to demonstrate the electrical continuity of the silicon–diamond interface after the bonding.

Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Silicon-on-diamond (SOD) wafers potentially present thermal advantages over standard silicon-on-insulator (SOI) counterparts based on SiO2 as the buried insulating layer. This work reports the fabrication of high quality SOD wafers by the bond and etch back SOI process. One key parameter in the CVD diamond growth process is the substrate temperature. We focused here on two processes based on either high or low processing temperature to produce nanocrystalline diamond (NCD) on silicon. Both type of NCD films have been analyzed via Raman spectroscopy. Results have been correlated with scanning electron microscopy observations. In a second part, SOD wafers are fabricated and the crystalline quality of the active silicon layer is assessed via Raman measurements and high resolution transmission electron microscopy imaging. It is shown that the growth of diamond did not induce any structural defect or strain in the thin top silicon layer. Eventually, we demonstrate the efficiency of diamond integration thanks to micro-Raman spectroscopy, where the probing laser simultaneously generates Raman signal and controlled local heating. Our SOD wafers evidence a thermal resistance reduction of about 70% compared to conventional SOI materials, with heat source spatial extension in the micron range.

Optimization of Hybrid Silicon Microring Lasers

In this paper, we review the recent optimization work in hybrid silicon microring lasers. Device structure and fabrication procedures are discussed first, followed by two major improvements in carrier injection and thermal management. A simple, well-controlled quantum well undercut leads to about 20% enhancement of injection efficiency. A silicon-on-diamond (SOD) substrate is demonstrated to fundamentally solve the device heating issue for silicon-on-insulator (SOI)-based active devices. SOD rib waveguides show low propagation loss of 0.74 dB/cm, which is 0.2 dB/cm higher than SOI counterparts. More than 22× reduction of device heating in hybrid silicon microring lasers is projected by simulations.

Fabrication of Silicon-on-Diamond Substrate and Low-Loss Optical Waveguides

A simple, complementary metal-oxide-semiconductor (CMOS)-compatible fabrication technique is developed to demonstrate a robust silicon-on-diamond (SOD) substrate. The 2.5 μm × 700 nm waveguides with a spiral structure are fabricated on both SOD and conventional silicon-on-insulator (SOI) substrates, showing 0.74- and 0.54-dB/cm propagation loss, respectively. Finite element method (FEM) thermal simulation shows over 3× improvement in heat dissipation on a hybrid silicon laser structure when Si substrate is not a limiting factor.

Progress towards III‐nitrides HEMTs on free‐standing diamond substrates for thermal management

AbstractIn this paper, we discuss the progress in the application of silicon‐on‐diamond (SOD) and chemically vapour deposited (CVD) diamond wafers as an alternative solution to silicon and silicon carbide (SiC) substrates to enhance heat dissipation away from the active region of AlGaN/GaN high electron mobility transistors (HEMT) while decreasing thermal degradation due to thermal effects. The superior thermal conductivity and insulating properties of polycrystalline diamond (8–15 Wcm/K) free‐standing wafers have demonstrated certain advantages, mostly evident in the device performance and reliability. Two unique diamond growth applications engineered by sp3 Diamond Technologies Inc., and Group4 Labs Inc., are discussed and device performance data is presented from early attempts to our most current device research efforts. As single‐crystalline diamond wafers (∼20 Wcm/K) become more accessible and affordable, it is expected to see significant improvement over the current state of this technology.magnified image Group4 employs an atomic bonding process of the AlGaN/GaN layers onto a polycrystalline CVD diamond wafer while sp3 grows the AlGaN/GaN layers on a thin silicon template layer which covers the diamond.

Silicon-On-Diamond layer integration by wafer bonding technology

In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management. We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200 nm to 7000 nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50 mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5 µm thick diamond layer could be reduced from 50 to 3 nm RMS and down to 1.5 nm RMS for a thin 200 nm layer. In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC. Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70 nm) of 50 mm diameter onto a 140 nm thick diamond BOX layer has been transferred on 200 mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.

Extreme insulating ultrathin diamond films for SOD applications: From coalescence modelling to synthesis

The synthesis of diamond films with extreme insulating properties is of great interest for most diamond film applications in nanoelectronics. SOD (Silicon-On-Diamond) is a promising alternative to standard SOI (Silicon-On-Insulator) because of the high heat-spreading capability of diamond material. Current Fully Depleted MOS processing technologies require a thickness of the dielectric buried layer of 150 nm. Synthesis of polycrystalline diamond films is already well documented. Nonetheless, the difficulties here are to keep their high thermal conductivity and their high electrical resistivity in spite of the reduction of the diamond layer thickness. This study aims at the fine control of both the nucleation density and the growth process to enable the fabrication of optimized fully covered diamond films as thin as possible. A mathematical model describing the coalescence was used to determine the surface coverage of the diamond film according to the linear growth of the diamond nanocrystals for different nucleation densities. The model gives information on the nucleation density needed to obtain a covering diamond film within ultrathin diamond layer thickness. To corroborate the coalescence model, diamond layers with different surface coverages were characterized. Our work led to ultrathin diamond layers (thickness below 140 nm) exhibiting electrical resistivities above 2 × 10 13 Ω cm.

Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut™ technology

In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and Etched-back SOI) and the Smart-Cut™ process. The polycrystalline diamond (C∗) film deposited by Chemical Vapor Deposition assisted by Microwave Plasma (MPCVD) was planarized by an innovative process which induces a significant decrease of the diamond surface roughness (1.2nm for the 200nm diamond layer). The planarization method as well as the entire SOD substrate process by the BESOI or the Smart-Cut™ technology are described in the paper. Cross sectional high-resolution transmission microscopy reveals the good quality of the future silicon channel on top of the thin diamond layer.

Comparative study of textured diamond films by thermal conductivity measurements

Superior thermal conductivity, high resistance, high breakdown voltage and wide band gap make diamond an attractive material for a variety of applications in electronics. One of its most appealing applications is as a buried dielectric in silicon-on-diamond (SOD) technology. This paper presents thermal conductivity measurements conducted on a series of diamond films (grown by the microwave plasma chemical vapor deposition technique) as a function of the sample morphology and thickness, for eventual incorporation in the SOD structures. Results show that there is a significant difference in the measured thermal conductivity between samples with fiber texture and samples with sheet texture. Also, measurements performed on a 160-μm-thick diamond sample before and after reactive ion etching of approximately 10 μm of the nucleation layer show no significant change in the measured value of the thermal conductivity.

Enhancing Semiconductors with Diamond

ABSTRACTIn the continuing thrust to extend Moore's law, silicon is beginning to confront several issues that require innovative materials solutions to increase transistor and interconnect speeds while dealing with the increasing thermal loads of advanced microprocessors. The unsurpassed thermal and mechanical properties of diamond can be profitably exploited to enhance the performance characteristics of silicon based circuits. The discussion focuses primarily on the integration of diamond with silicon for the manufacture of silicon on diamond (SOD) wafers for spreading heat from hot spots in microprocessors. Other interesting property combinations are also presented as food for thought regarding other possible enhancements to silicon device performance. Recent data and prognosis for the future will be presented.

Synthesis of sub-micron diamond films on Si(100) for thermal applications by BEN-MPCVD

ABSTRACTDiamond is the ultimate candidate for heat-spreading applications because of its extreme thermal management properties. The synthesis of sub-micron diamond films is of great interest for SOD (Silicon On Diamond) wafer technology as well as for specific thermal device applications. The challenge here is the necessity to fabricate ultra-thin layers (down to 100 nm) that are continuous and homogeneous. We studied the Bias Enhanced Nucleation (BEN) pretreatment on microwave plasma reactors in order to have very high nucleation densities (> to 1011 cm−2) and optimised the following growth step of the process to obtain sub-micron covering diamond films. In this study, we focus on the bias step parameters to increase the nucleation rate and to limit the growth rate during the bias step. Then, we performed a growth step to control the morphology of the films. We obtained diamond films with thickness lower than 80 nm and with a 6 nm Root-Mean-Square roughness.

Silicon-on-Diamond — An engineered substrate for electronic applications

Silicon on Diamond (SOD) is a substrate engineered to address the major challenges of silicon-based ULSI technology, in particular, to provide for enhanced thermal management and charge confinement. The SOD concept is achieved by joining a thin, single crystalline Si device layer to a highly oriented diamond (HOD) layer that serves as an electrical insulator, heat spreader and supporting substrate. Therefore, SOD represents an alternative SOI concept, where the thermally insulating SiO 2 has been replaced by highly thermally conductive diamond. Initial experiments and theoretical assessments have been aimed at demonstrating the improved thermal management properties of fabricated SOD wafers and comparing them to Si and SOI [A. Aleksov, X. Li, N. Govindaraju, J.M. Gobien, S.D. Wolter, J.T. Prater, Z. Sitar, Silicon on Diamond: an advanced Silicon on Insulator technology, Diamond and Related Materials, 14, 308–313 (2005).], [A. Aleksov, S.D. Wolter, J.T. Prater, Z. Sitar, Fabrication and Thermal Evaluation of Silicon on Diamond Wafers, Journal of Electronic Materials, 34 (2005) 1089.]. The experimental results are in good agreement with the values obtained by finite element modeling (FEM). The results show that for a 1.5 μm thick Si device layer, SOD can sustain more than 10 times higher power than SOI. This in turn will permit a more than 3-fold greater integration density of circuits fabricated on SOD as compared to SOI. Having validated the superior thermal management properties of SOD, the second task has been to compare device operation on SOD and SOI to identify whether the Si layer degrades during the SOD fabrication process. In addition, the analysis of the interface properties between the Si device layer and diamond is important in order to better understand the operation of devices on SOD and identify their limitations. For this reason, Schottky and pn-junction diodes were fabricated on the Si device layer of SOD and SOI wafers. The first results of the electrical analyses indicated that there are no additional leakage currents in SOD devices compared to devices on SOI. In addition, CV measurements indicated no differences in the device behavior i.e. no additional charge trapping with respect to SOI in the frequency range of 1 kHz–10 MHz.

Thermal stability of diamondlike carbon buried layer fabricated by plasma immersion ion implantation and deposition in silicon on insulator

Diamondlike carbon (DLC) as a potential low-cost substitute for diamond has been extended to microelectronics and we have demonstrated the fabrication of silicon on diamond (SOD) as a silicon-on-insulator structure using plasma immersion ion implantation and deposition in conjunction with layer transfer and wafer bonding. The thermal stability of our SOD structure was found to be better than that expected for conventional DLC films. In the work reported here, we investigate the mechanism of the enhanced thermal stability. We compare the thermal stability of exposed and buried DLC films using Raman spectroscopy and x-ray photoelectron spectroscopy (XPS). Our Raman analysis indicates that the obvious separation of the D and G peaks indicative of nanocrystalline graphite emerges at 500°C in the exposed DLC film. In contrast, the separation appears in the buried DLC film only at annealing temperatures above 800°C. Analysis of the XPS C1s core-level spectra shows that the (sp3+C–H) carbon content of the unprotected DLC film decreases rapidly between 300–700°C indicating the rapid transformation of sp3-bonded carbon to sp2-bonded carbon combined with hydrogen evolution. In comparison, the decrease in the (sp3+C–H) carbon content of the buried DLC film is slower below 800°C. Elastic recoil detection results show that this superior thermal stability is due to the slower hydrogen out diffusion from the buried DLC film thereby impeding the graphitization process. We propose that the SiO2 overlayer retards the graphitization process during annealing by shifting the chemical equilibrium.

Fabrication and thermal evaluation of silicon on diamond wafers

Silicon on diamond (SOD) is proposed as a superior alternative to conventional silicon on insulator (SOI) technology for silicon-based electronics. In this paper, we present a novel SOD structure in which the active Si layer is in direct contact with a thick, highly oriented diamond (HOD) layer that is directly attached to a heat sink. In contrast to the earlier work,1,2 the diamond film is relatively thick (∼70 µm), free standing, and close to single crystalline, thus possessing much greater thermal conductivity and no limitation of the Si backing wafer. Two different fabrication schemes are investigated: (1) direct growth, where the Si-device layer makes contact with the nucleation side of the diamond layer; and (2) wafer fusion, where the Si device layer makes a direct contact with the diamond growth surface. Thermal evaluation was performed using metallic microheaters. These studies clearly showed more than one order of magnitude better thermal management properties of diamond with respect to Si and SOI.