Silicon-On-Diamond layer integration by wafer bonding technology

Abstract

In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management. We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200 nm to 7000 nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50 mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5 µm thick diamond layer could be reduced from 50 to 3 nm RMS and down to 1.5 nm RMS for a thin 200 nm layer. In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC. Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70 nm) of 50 mm diameter onto a 140 nm thick diamond BOX layer has been transferred on 200 mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.