Silicon Deep Reactive Ion Etching Research Articles

Deep-reactive ion etching of silicon nanowire arrays at cryogenic temperatures

The pursuit of sculpting materials at increasingly smaller and deeper scales remains a persistent subject in the field of micro- and nanofabrication. Anisotropic deep-reactive ion etching of silicon at cryogenic temperatures (cryo-DRIE) was investigated for fabricating arrays of vertically aligned Si nanowires (NWs) of a large range of dimensions from micrometers down to 30 nm in diameter, combined with commonly used wafer-scale lithography techniques based on optical, electron-beam, nanoimprint, and nanosphere/colloidal masking. Large selectivity of ∼100 to 120 and almost 700 was found with resists and chromium hard masks, respectively. This remarkable selectivity enables the successful transfer of patterned geometries while preserving spatial resolution to a significant extent. Depending on the requirements by applications, various shapes, profiles, and aspect ratios were achieved by varying process parameters synchronously or asynchronously. High aspect ratios of up to 100 comparable to the best result by metal-assisted wet-chemical etching and sub-μm trenches by DRIE were obtained with NW diameter of 200 nm, at an etch rate of ∼4 μm/min without being collapsed. At the same time, low surface roughness values were maintained on the NW top, sidewall, and bottom surface of ∼0.3, ∼13, and ∼2 nm, respectively, as well as high pattern fidelity and integrity, which were measured using angle-resolved Fourier microscopy, combined atomic force, and scanning electron microscopy on selected NWs. This work establishes the foundation in the controllable development of Si nanoarchitectures, especially at sub-100 nm structures, for energy-harvesting and storage, damage-free optoelectronics, quantum, photovoltaics, and biomedical devices.

Wafer-scale silicon microfabrication technology toward realization of low-cost sub-THz waveguide devices

This paper presents a wafer-scale silicon microfabrication technology for the sub-terahertz (sub-THz) waveguide device mass production. Based on the effective scheme, a WR-5 (140–220 GHz) straight rectangular waveguide and a WR-2.8 (260–400 GHz) rectangular waveguide bandpass filter are implemented as demonstrated examples. The silicon deep reactive ion etching (DRIE) process is employed to etch through the total thickness of the silicon wafer and form the main waveguide channels. Then, a low-temperature thermal compression process is used to bond the trough-etched wafer with the top and bottom metallised silicon wafers to form the closed waveguide structures without any precise alignment process. The fabricated waveguide has the benefit of low transmission loss (0.03–0.05 dB mm−1) at the whole G band. Besides, to measure the fabricated WR-2.8 waveguide filter and solve the measuring equipment standard waveguide difference, silicon micromachined waveguide transitions are explored and fabricated to match two different frequency-band modules for measuring the waveguide filters in the desired full frequency band, which also has a potential application for the different size waveguide conversion. The measured results agree well with the simulated ones. The measured 3 dB bandwidth is 9.3%, with a central frequency of 343 GHz; the average insertion loss (IL) is about 1.6 dB in the pass band, including two extra straight waveguides of 8 mm length on input/output ends and two external waveguide-to-waveguide transitions. The proposed method provides a feasible and cost-effective solution for the mass production of high-performance waveguide devices and integrated systems in sub-THz frequency bands and beyond.

Fabrication of a transparent array of penetrating 3D microelectrodes with two different heights for both neural stimulation and recording

Microelectrode array (MEA) is one of the representative platforms for recording and stimulating neurons to explore their populational electrophysiological activities. Due to the layered structures of the nervous system, various three-dimensional (3D) MEAs have been used to reach specific target depths of neuronal tissues. But it is still difficult to monolithically fabricate various heights of microelectrodes, particularly with optical transparency. Here, we present a 3D MEA with different heights fabricated by multi-step silicon deep reactive ion etching. The microelectrodes were embedded in reflowed glass for high transparency which enables both neural tissue observation and optical stimulation. The heights of microelectrodes were well controlled by our fabrication processes and electrical connections were made with through glass vias (TGVs) to the bottom side for individual addressing. To confine electric stimulation in a small area, we used microelectrodes neighboring a stimulation electrode as local returns. The feasibility of the fabricated MEA was demonstrated by stimulating the mouse retina and successfully recording spikes of ganglion cells located near the stimulation site. Consistent with our COMSOL simulation, the ex vivo experimental results showed the stimulation current confinement was effective. Our study provides a new tool for 3D nervous systems and its fabrication method.

Terahertz Barcodes Enabled by All‐Silicon Metasurfaces for Process Control and Monitoring Applications

AbstractProcess control and monitoring (PCM) is crucial for the quality control and yield improvement of semiconductor products. Terahertz inspection of semiconductor devices has been of interest since the progress of terahertz spectroscopic techniques. However, due to the diffraction limit, high‐resolution measurement of geometric sizes and multiple parameter monitoring are challenging for terahertz PCM techniques. In this article, XX present terahertz all‐dielectric metasurfaces as the interface on a silicon substrate for monitoring material properties and fabrication errors in the silicon deep reactive ion etching (DRIE) process. It is shown that four different metasurfaces can encode multiple information simultaneously, including the carrier density of silicon substrates, etching depth and linewidth error, forming a terahertz barcode for PCM. By correlating the measured reflection spectra of the barcode with those in the simulation database, the three parameters are retrieved with a mean square error (MSE) of ≈0.5. The results indicate that this proposed technique using emerging artificial photonic materials as PCM structures paves a pathway toward high‐efficiency semiconductor quality control and other sensing applications.

Fabrication of Substrate-Integrated Waveguide Using Micromachining of Photoetchable Glass Substrate for 5G Millimeter-Wave Applications

A millimeter-wave substrate-integrated waveguide (SIW) was firstly demonstrated using the micromachining of photoetchable glass (PEG) for 5G applications. A PEG substrate was used as a dielectric material of the SIW, and its photoetchable properties were used to fabricate through glass via (TGV) holes. Instead of the conventional metallic through glass via (TGV) array structures that are typically used for the SIW, two continuous empty TGV holes with metallized sidewalls connecting the top metal layer to the bottom ground plane were used as waveguide walls. The proposed TGV walls were fabricated by using optical exposure, heat development and anisotropic HF (hydrofluoric acid) etching of the PEG substrate, followed by a metal sputtering technique. The SIW was fed by microstrip lines connected to the waveguide through tapered microstrip-to-waveguide transitions. The top metal layer, including these feedlines and transitions, was fabricated by selective metal sputtering through a silicon shadow mask, which was prefabricated by a silicon deep-reactive ion-etching (DRIE) technique. The developed PEG-based process provides a relatively simple, wafer-level manufacturing method to fabricate the SIW in a low-cost glass dielectric substrate, without the formation of individual of TGV holes, complex time-consuming TGV filling processes and repeated photolithographic steps. The fabricated SIW had a dimension of 6 × 10 × 0.42 mm3 and showed an average insertion loss of 2.53 ± 0.55 dB in the Ka-band frequency range from 26.5 GHz to 40 GHz, with a return loss better than 13.86 dB. The proposed process could be used not only for SIW-based devices, but also for various millimeter-wave applications where a glass substrate with TGV structures is required.

2.4 ng/√Hz low-noise fiber-optic MEMS seismic accelerometer.

This paper introduces a fiber-optic microelectromechanical system (MEMS) seismic-grade accelerometer that is fabricated by bulk silicon processing using photoresist/silicon dioxide composite masking technology. The proposed sensor is a silicon flexure accelerometer whose displacement transduction system employs a light intensity detection method based on Fabry-Perot interference (FPI). The FPI cavity is formed between the end surface of the cleaved optical fiber and the gold-surfaced sidewall of the proof mass. The proposed MEMS accelerometer is fabricated by one-step silicon deep reactive ion etching with different depths using the composite mask, among which photoresist is used as the etching-defining mask for patterning the etching area while silicon dioxide is used as the depth-defining mask. Noise evaluation experiment results reveal that the overall noise floor of the fiber-optic MEMS accelerometer is 2.4 ng/H z at 10 Hz with a sensitivity of 3165 V/g, which is lower than that of most reported micromachined optical accelerometers, and the displacement noise floor of the optical displacement transduction system is 208 fm/H z at 10 Hz. Therefore, the proposed MEMS accelerometer is promising for use in high-performance seismic exploration applications.

A 135–150-GHz Frequency Tripler Using SU-8 Micromachined WR-5 Waveguides

This article presents a 135–150-GHz Schottky diode-based bias-less frequency tripler based on SU-8 micromachined WR-5 waveguides. The waveguides consist of five 432- $\mu \text{m}$ -thick silver-plated SU-8 layers, which house the diode chip and form the output matching network. The input matching circuit is realized in a computer numerical control (CNC) milled waveguide filter, which also provides support and thermal sink to the SU-8 waveguides. Considering the low thermal conductivity of the SU-8 material, auxiliary metallic thermal paths are designed, and the impact of these is discussed through thermal modeling. The thermal simulations show that under 50-mW power dissipation in the diode anodes, the maximum temperature of the SU-8 tripler is predicted to be 346 K at the diode junction, only 7 K higher than in an entirely metal equivalent. The tripler was measured to have a conversion loss of 16–18 dB and the input return loss is better than 18 dB. This work demonstrates that SU-8 micromachined waveguides can be used to package high-frequency semiconductor components, which, like other photolithography-based processes such as silicon deep reactive ion etching (Si-DRIE), has the potential for submicrometer feature resolution.

Fabrication and testing of PMOS current mirror-integrated MEMS pressure transducer

PurposeThis paper aims to describe the fabrication, packaging and testing of a resistive loadedp-channel metal-oxide-semiconductor field-effect transistor-based (MOSFET-based) current mirror-integrated pressure transducer.Design/methodology/approachUsing the concept of piezoresistive effect in a MOSFET, three identicalp-channel MOSFETs connected in current mirror configuration have been designed and fabricated using the standard polysilicon gate process and microelectromechanical system (MEMS) techniques for pressure sensing application. The channel length and width of thep-channel MOSFETs are 100 µm and 500 µm, respectively. The MOSFET M1 of the current mirror is the reference transistor that acts as the constant current source. MOSFETs M2 and M3 are the pressure-sensing transistors embedded on the diaphragm near the mid of fixed edge and at the center of the square diaphragm, respectively, to experience both the tensile and compressive stress developed due to externally applied input pressure. A flexible square diaphragm having a length of approximately 1,000 µm and thickness of 50 µm has been realized using deep-reactive ion etching of silicon on the backside of the wafer. Then, the fabricated sensor chip has been diced and mounted on a TO8 header for the testing with pressure.FindingsThe experimental result of the pressure sensor chip shows a sensitivity of approximately 0.2162 mV/psi (31.35 mV/MPa) for an input pressure of 0-100 psi. The output response shows a good linearity and very low-pressure hysteresis. In addition, the pressure-sensing structure has been simulated using the parameters of the fabricated pressure sensor and from the simulation result a pressure sensitivity of approximately 0.2283 mV/psi (33.11 mV/MPa) has been observed for input pressure ranging from 0 to 100 psi with a step size of 10 psi. The simulated and experimentally tested pressure sensitivities of the pressure sensor are in close agreement with each other.Originality/valueThis current mirror readout circuit-based MEMS pressure sensor is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

Scalable Superomniphobic Surfaces

Superomniphobic surfaces that repel liquids of extremely low surface tension rely on carefully fabricated doubly re-entrant topographies, typically made by silicon deep reactive ion etching technology. However, previously published processes have depended on critically timed etching steps, which are difficult to downscale. We present a scalable process that eliminates the critically timed etching steps. It is based on the use of silicon-on-insulator wafers and a silicon oxide foot of the micropillar, which makes the isotropic silicon release step non-critical. The process allows easy downscaling of pillars from 20 $\mu \text{m}$ to 10 $\mu \text{m}$ and $5~\mu \text{m}$ . The downscaling increases the stability of the Cassie state. Based on the process, we are able to create superomniphobic surfaces that sustain perfluorohexane (FC-72), which has the lowest surface tension of the known liquids at room temperature ( $\gamma _{\text {lv}}=11.91$ mN/m at 20 °C), in the Cassie state at droplet diameters down to 200 micrometers. These are the smallest perfluorohexane droplets repelled to date. [2019-0207]

Silicon Deep Reactive Ion Etching with aluminum hard mask

Silicon Deep Reactive Ion Etching (DRIE) process using a multi-layer mask containing a sputtered Aluminum thin film is studied. Aluminum is a candidate for very high aspect ratio DRIE, due to tis very low etch rate, but its adoption is hindered by the presence of micromasking. Effects of adding aluminum as the middle layer in a stack of silicon oxides are studied: heat dissipation and catalyst contribution to plasma chemistry are identified. The novel assumption that micromasking is generated only in the first part of the DRIE etching is demonstrated. Based on this, the effect of adding a protective coating on top of the mask is studied. The protective coating preserves aluminum in the first part of the etching, to reach a given depth before the aluminum mask is exposed to the etching plasma. A Safe aspect ratio value is obtained, beyond which micromasking does not take place. This aspect ratio is shown to be a function of the etching geometry and feature size.

Precision Au Electrocoating of Double Sided Aligned Si Gratings for High Energy X-Ray Phase Contrast Imaging

State of the art grating fabrication currently limits the maximum source energy that can be used in lab based x-ray phase contrast imaging (XPCI) systems. In order to move to higher source energies, and image thicker and more dense materials, new grating fabrication methods are needed. In previous work we developed a differentiating mold construction technique that replaces photodefinable organic templates1 with high aspect ratio silicon (Si) deep reactive ion etching (DRIE) followed by precision electrodeposition of gold (Au)2. Combining DRIE with precision electro-coating enabled the fabrication of un-supported Au absorption gratings with aspect ratios as high as 50:1 and grating areas as large as 100 cm2. Further pushing this grating fabrication to enable the use of higher energy x-ray sources, we developed a new modality for grating fabrication that involves precision alignment of etched features on both sides of a substrate, effectively doubling the thickness of the. This double sided grating fabrication approach was applied to make a phase grating out of DRIE Si. In this work, we couple double sided Si DRIE with precision gold (Au) electrodeposition to fabricate absorption gratings for high energy lab based XPCI. A 250 µm deep, 2 µm wide, and 4 µm pitch absorption grating was fabricated by aligning and etching 125 µm deep grating features on both sides of a Si wafer. The Si grating features are patterned and etched on an 8 µm pitch with the width of the Si features patterned at 2 µm. Fabricating uniform, high aspect ratio features across large areas on both sides of a substrate is difficult due to the need to temporarily protect one side of the grating while processing on the opposite side of the substrate. After both sides are processed, this temporary support material must be removed without damaging the gratings on either side of the substrate. At these feature sizes, surface tension forces after wet processing are strong enough to collapse the grating features and must be carefully avoided. Our integration approach for accommodating these challenges is illustrated in Figure 1. Alignment features are first patterned and etched into both sides of the substrate. The front side gratings are then patterned with reference to the front side field image alignment marks and etched into the Si. Plasma enhanced tetraethylorthosilicate (PETEOS) SiO2 is then deposited to protect the front side gratings during backside processing. The backside gratings are similarly aligned using the alignment marks on the backside of the substrate. After the gratings on both sides of the substrate are etched, a selective wet etch is used to remove the supportive oxide and a critical point dryer is used to prevent surface tension forces from damaging the Si bars. A conformal platinum (Pt) plating seed metal is deposited by atomic layer deposition (ALD) and Au is precisely electroplated at a uniform thickness of 2 μm throughout the depth of the Si grating. The Au serves as a high x-ray absorbing material finalizing the fabrication process. In this work, we provide details on our fabrication approach and measurements of our final grating geometries. Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. [1] - High Aspect Ratio Gratings for X-Ray Phase Contrast Imaging: J. Mohr, T. Grund, D. Kunka, J. Kenntner, J. Leuthold, J. Meiser, J. Schulz and M. Walter, International Workshop on X-Ray and Neutron Phase Imaging with Gratings, Tokyo, Japan, 2012; [2] - Extensively long high aspect ratio gold analyzer gratings: A. E., Hollowell, C. L. Arrington, J. J. Coleman, P. S. Finnegan, A. M. Rowen, and A. L. Dagel, X-ray and Neutron Phase Imaging with Gratings, Bethesda, MD, 2015 [3] – Double Sided Grating Fabrication for High Energy X-Ray Phase Contrast Imaging: A. E. Hollowell, C. L. Arrington, P. Finnegan, K. Musick, P. Resnick, S. Volk, and A. L. Dagel, Material Science in Semiconductor Processing, 2018, under review. Figure 1

The effect of increasing interfacial strength in micro fluidic system for heat detection with micro-sandglass shaped interlocks

We present a useful method to increase interfacial strength for micro fluidic system of calorimetry biosensor. The micro-sandglass shaped posts were fabricated by deep silicon reactive ion etching and Tetramethyl ammonium hydroxide (25 wt% TMAH) anisotropic etching processes, sequentially. The interfacial strength can be controlled by structure of interlock which dependents on the TMAH etching time and diameter of micro pillar. The fabricated micro-standglass shaped interlocks were applied in micro fluidic structure to increase interfacial strength of micro fluidic structure. The detection result of reactive heat using calorimetry biosensor demonstrates that the interfacial strength can be increased by micro-standglass shaped interlocks to avoid leakage in micro fluidic system.

Knudsen pump produced via silicon deep RIE, thermal oxidation, and anodic bonding processes for on-chip vacuum pumping

This work describes the fabrication and evaluation of the Knudsen pump for on-chip vacuum pumping that works based on the principle of a thermal transpiration. Three AFM (atomic force microscope) cantilevers are integrated into small chambers with a size of 5 mm × 3 mm × 0.4 mm for the pump’s evaluation. Knudsen pump is fabricated using deep RIE (reactive ion etching), wet thermal oxidation and anodic bonding processes. The fabricated device is evaluated by monitoring the quality (Q) factor of the integrated cantilevers. The Q factor of the cantilever is increased from 300 –1150 in cases without and with a temperature difference approximately 25 °C between the top (the hot side at 40 °C) and bottom (the cold side at 15 °C) sides of the fabricated device, respectively. The evacuated chamber pressure of around 10 kPa is estimated from the Q factor of the integrated cantilevers.

Development of Minimal Si-DRIE Tool and Process Performance

The expertise of SPP Technologies in plasma processing techniques has led to the company`s cooperation in the “minimal fab” concept proposed by AIST. A Bosch process deep silicon reactive ion etching process chamber has been developed. A plasma with similar properties to those generated in a mass-production process chamber has been realized in a minimal fab process chamber. Design and evaluation of the minimal process chamber was performed by plasma and radical characterization. Successful process results were achieved by generating a plasma with similar density and bias energy to that of a mass production chamber. SPP Technologies has achieved the first Si-DRIE minimal process chamber using the Bosch process. SPT's Minimal Si-DRIE chamber, a research platform aimed at IoT, AI, and other MEMS devices, can be expected to make a big impact due to its early release.

Resonant pitch and roll silicon gyroscopes with sub-micron-gap slanted electrodes: Breaking the barrier toward high-performance monolithic inertial measurement units

This paper presents the design, fabrication, and characterization of a novel high quality factor (Q) resonant pitch/roll gyroscope implemented in a 40 μm (100) silicon-on-insulator (SOI) substrate without using the deep reactive-ion etching (DRIE) process. The featured silicon gyroscope has a mode-matched operating frequency of 200 kHz and is the first out-of-plane pitch/roll gyroscope with electrostatic quadrature tuning capability to fully compensate for fabrication non-idealities and variation in SOI thickness. The quadrature tuning is enabled by slanted electrodes with sub-micron capacitive gaps along the (111) plane created by an anisotropic wet etching. The quadrature cancellation enables a 20-fold improvement in the scale factor for a typical fabricated device. Noise measurement of quadrature-cancelled mode-matched devices shows an angle random walk (ARW) of 0.63° √h−1 and a bias instability of 37.7° h−1, partially limited by the noise of the interface electronics. The elimination of silicon DRIE in the anisotropically wet-etched gyroscope improves the gyroscope robustness against the process variation and reduces the fabrication costs. The use of a slanted electrode for quadrature tuning demonstrates an effective path to reach high-performance in future pitch and roll gyroscope designs for the implementation of single-chip high-precision inertial measurement units (IMUs).

Polymer bonding of GaN crystal layer on silicon substrate for micro mechanical resonator applications

A polymer bonding method of GaN crystal layer on silicon substrate is proposed for the integration of GaN micro electromechanical devices on silicon substrate. A GaN crystal layer is grown on a silicon wafer epitaxially with a buffer layer. Avoiding the influence of residual stress of the buffer layer on the GaN micro electromechanical devices, the GaN layer is transferred onto another silicon wafer by the polymer bonding method and the buffer layer is removed. The bonding method consists of two-step polymer process to prevent from breaking the bonded GaN thin layer by air bubbles. The polymer is patterned to generate air channels in the first polymer process so that the air bubbles are not remained after bonding the GaN/silicon wafer. The air channels are filled with another polymer in the second polymer process. Then, the silicon substrate of the GaN/silicon wafer is removed by silicon deep reactive ion etching, and the buffer layer for GaN crystal growth is also etched by fast atom beam of SF6 plasma and Cl2 reactive ion plasma. The bonded GaN layer is used for fabricating GaN micro mechanical resonators on silicon substrate by etching the polymers as sacrificial layer. The deformation of the freestanding resonator was minimized by removing the buffer layer. A cantilever resonator fabricated from GaN layer is excited by optical means and the basic characteristics are discussed.

A Multistep DRIE Process for Complex Terahertz Waveguide Components

A silicon deep reactive-ion etching (DRIE) process has been developed, using multiple SiO2 masks to enable multidepth waveguide features with ±2% tolerance. The unique capability of this process is demonstrated by designing, fabricating, and testing an orthomode transducer working in the 500–600 GHz frequency range. Straight waveguide measurements are also performed to characterize the losses associated with the multistep DRIE process, giving results slightly better than expected for metal-machined waveguides. This process enables the integration of multiple terahertz waveguide components such as mixers, multipliers, quadrature hybrids, and polarization twists onto a single silicon package.

Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of <TEX>$1.04{\times}1.04{\times}0.4mm^3$</TEX> had an average shear strength of 10.425 <TEX>$kg/mm^2$</TEX>, and the leakage rate of all chips was lower than <TEX>$1.2{\times}10^{-5}$</TEX> atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

Vertical finFET with Salicide Contact for Potential Power Applications

We report a vertically diffused finFET with high-κ gate dielectric and metal gate for potential power applications. Electron beam lithography and deep silicon reactive ion etching (RIE) were utilized to form the fins, followed by atomic layer deposition of Al2O3 high-k dielectric and TiN to form the metal gate. Self-aligned silicide (salicide) was formed on the top of the fins to lower the contact resistance. The devices exhibit excellent performance with steep sub-threshold swing (SS), low drain-induced barrier lowering (DIBL) and a high ION/IOFF ratio. The breakdown voltage test (BVDSS) was also characterized for potential power applications.

Silicon Germanium as a Novel Mask for Silicon Deep Reactive Ion Etching

This paper reports on the use of p-type polycrystalline silicon germanium (poly-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) thin films as a new masking material for the cryogenic deep reactive ion etching (DRIE) of silicon. We investigated the etching behavior of various poly-Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> :B (0<;x<; 1) thin films deposited at a wide temperature range (250°C to 600 °C). Etching selectivity for silicon, silicon oxide, and photoresist was determined at different etching temperatures, ICP and RF powers, and SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ratios. The study demonstrates that the etching selectivity of the SiGe mask for silicon depends strongly on three factors: Ge content; boron concentration; and etching temperature. Compared to conventional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiN masks, the proposed SiGe masking material exhibited several advantages, including high etching selectivity to silicon (>1:800). Furthermore, the SiGe mask was etched in SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma at temperatures ≥ - 80°C and at rates exceeding 8 μm/min (i.e., more than 37 times faster than SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or SiN masks). Because of the chemical and thermodynamic stability of the SiGe film as well as the electronic properties of the mask, it was possible to deposit the proposed film at CMOS backend compatible temperatures. The paper also confirms that the mask can easily be dry-removed after the process with high etching rate by controlling the ICP and RF power and the SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ratios, and without affecting the underlying silicon substrate. Using low ICP and RF power, elevated temperatures (i.e., > - 80°C), and an adjusted O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> :SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> ratio (i.e., ≈ 6%), we were able to etch away the SiGe mask without adversely affecting the final profile. Ultimately, we were able to develop deep silicontrenches with high aspect ratio etching straight profiles.