Silicon Chip Research Articles

A Novel End-to-End Deep Learning Framework for Chip Packaging Defect Detection.

As semiconductor chip manufacturing technology advances, chip structures are becoming more complex, leading to an increased likelihood of void defects in the solder layer during packaging. However, identifying void defects in packaged chips remains a significant challenge due to the complex chip background, varying defect sizes and shapes, and blurred boundaries between voids and their surroundings. To address these challenges, we present a deep-learning-based framework for void defect segmentation in chip packaging. The framework consists of two main components: a solder region extraction method and a void defect segmentation network. The solder region extraction method includes a lightweight segmentation network and a rotation correction algorithm that eliminates background noise and accurately captures the solder region of the chip. The void defect segmentation network is designed for efficient and accurate defect segmentation. To cope with the variability of void defect shapes and sizes, we propose a Mamba model-based encoder that uses a visual state space module for multi-scale information extraction. In addition, we propose an interactive dual-stream decoder that uses a feature correlation cross gate module to fuse the streams' features to improve their correlation and produce more accurate void defect segmentation maps. The effectiveness of the framework is evaluated through quantitative and qualitative experiments on our custom X-ray chip dataset. Furthermore, the proposed void defect segmentation framework for chip packaging has been applied to a real factory inspection line, achieving an accuracy of 93.3% in chip qualification.

Numerical Investigation on the Influence of Substrate Board Thermal Conductivity on Electronic Component Temperature Regulation

This study presents a detailed numerical analysis of substrate boards made from various materials (FR-4, Si cladding, and Cu cladding) with nine electronic components mounted on them. Each component is subjected to different heat fluxes, and the analysis covers both natural convection (NC) and forced convection (FC) modes of heat transfer at air velocities of 4m/s and 6m/s. The findings reveal that at an air velocity of 6m/s, using a copper cladding board significantly lowers the temperatures of the electronic components by 340C to 540C compared to FR-4 and Si cladding boards. Additionally, the copper cladding reduces the required air-cooling velocity by 2m/s and achieves a temperature reduction for the IC chips ranging from 3.500C to 13.120C. It is recommended to use an air velocity of 4m/s with copper cladding to minimize fan power consumption while maintaining component temperatures below 1250C. These results provide crucial insights for thermal design engineers, aiding in the selection of appropriate substrate boards for effective thermal management of electronic components. The study emphasizes the benefits of copper cladding in distributing heat more uniformly, reducing energy consumption, and maintaining optimal operating temperatures. Furthermore, it suggests that placing high heat-dissipating components at inlet or outlet points can minimize thermal interactions and overall configuration temperatures. The research offers valuable guidance to the heat transfer community, particularly electronic thermal designers, by highlighting the importance of substrate material choice and component placement in enhancing the reliability and lifespan of integrated circuits (ICs). The comprehensive analysis and recommendations serve as a vital resource for optimizing thermal control strategies in electronic devices, ultimately contributing to improved performance and durability.

Lifetime prediction of copper pillar bumps based on fatigue crack propagation

2.5D package realizes the interconnection of multiple dies through Si interposers, which can greatly improve the data transmission rate between dies. However, its multi-layer structure and high package density also place higher reliability requirements on the interconnection structure. As a key structure for interconnection, copper pillar bump (CPB) has small size, high heat generation, and thermal mismatch with silicon chips. The thermal fatigue failure of CPB has gradually become the main failure mode in 2.5D package. Due to the small size of CPB and the large proportion of intermetallic compound (IMC) layers, the lifetime prediction method of spherical solder joints is no longer suitable for CPB. Therefore, it is necessary to establish a fatigue lifetime prediction method for CPB. This paper establishes a method for obtaining the lifetime of CPB based on the basic theory of fatigue crack propagation. Using the extended finite element simulation method, the crack propagation lifetime of CPB under thermal cycling was obtained, and the influence of different IMC layer thickness on the fatigue lifetime of CPB was analyzed. The results indicated that the fatigue lifetime of cracks propagating in the IMC layer is lower than that of cracks propagating in the solder layer, and an increase in the thickness of the IMC layer leads to a significant decrease in the fatigue lifetime of CPB. The lifetime prediction method for CPB proposed in this paper can be used for reliability evaluation of 2.5D package, and has certain reference value for the study of the lifetime of CPB.

Effects of Diethoxymethylsilane/Helium Flow Rate Ratio on Low-k Films Deposited by Plasma-Enhanced Chemical Vapor Deposition

As the semiconductor industry has continuously reduced the integrated circuit (IC) chip size, a resistance-capacitance (RC) delay emerged, causing deterioration of the chip performance. To reduce the RC delay, low dielectric constant (low-k) films with suitable mechanical strengths have been adopted as intermetal dielectrics (IMDs). In this study, low-k plasma-polymerized diethoxymethylsilane (ppDEMS) films were fabricated by plasma-enhanced chemical vapor deposition of the DEMS precursor with a flow rate ratio of the DEMS precursor to helium (He) carrier gas (DEMS/He FRR) as a key parameter. As the DEMS/He FRR increased, the refractive index was reduced from 1.401 to 1.386, and the k value decreased from 2.77 to 2.10. From high-resolution scans of C1s, O1s, and Si2p peaks of X-ray photoelectron spectroscopy, the carbon contents increased, and the oxygen contents decreased, along with a decrease in the film density. With the increased DEMS/He FRR, hardness decreased from 2.5 to 1.8 GPa, and elastic modulus decreased from 17.08 to 11.50 GPa. Leakage current densities for all the ppDEMS films were less than 10−7 A cm−2 at 1 MV cm−1. The ppDEMS films could be suggested as the IMDs according to their electrical and mechanical performance.

Design and analysis of low power sense amplifier for static random access memory

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Cr-doped CdS and ZnS nano/microstructures with ferromagnetic properties

Transition-metal-doped cadmium sulfide (CdS) and zinc sulfide (ZnS) dilute magnetic semiconductors have attracted widespread research interests due to their potential spin electron applications. Most theoretical and experimental analyses have focused on studying their optical properties. In response to the widespread application of dilute magnetic semiconductor nanomaterials in electronic components, semiconductor chips, integrated circuits and other fields, dilute magnetic semiconductors with room-temperature ferromagnetic chromium (Cr)-doped cadmium sulfide and zinc sulfide nanostructures were synthesized using the solvothermal method. According to X-ray diffraction analysis, the products of chromium-doped cadmium sulfide and zinc sulfide were clearly determined to be a hexagonal phase. Scanning electron microscopy images showed that the morphologies of cadmium sulfide and zinc sulfide with different contents of chromium were mainly composed of nanorods and a micro-floral shape. Energy-dispersive X-ray spectroscopy measurements indicated that the synthesized products were composed of chromium, cadmium (Cd), zinc (Zn) and sulfur (S). Vibrating-sample magnetometry showed that undoped cadmium sulfide exhibited weak ferromagnetism at room temperature, and undoped zinc sulfide exhibited diamagnetism, while chromium-doped cadmium sulfide and zinc sulfide had strong ferromagnetism. The saturation magnetization M s of chromium-doped cadmium sulfide (chromium = 4.21%) was about 9.524 × 10−3 emu/g; the coercivity H c was about 98.327 Oe. The saturation magnetization M s of chromium-doped zinc sulfide (chromium = 7.67%) was about 8.502 × 10−3 emu/g; the coercivity H c was about 96.237 Oe. The ferromagnetism of chromium-doped cadmium sulfide and zinc sulfide was attributed to the double-exchange mechanism.

Twice-topology optimized heat sinks for enhanced heat transfer performance: Numerical and experimental investigation

Since the heat dissipation problem is always confusing and hindering the computing power improvement of electronic chip, an effective thermal management strategy is critical to relieve these problems. In this work, a new twice topology optimization design method combining topology optimization and image processing to design heat sinks is presented, which extends topology optimization from 2Dimention (2D) to 3Dimention(3D). Firstly, on the horizontal design domain, the conventional topology optimization is conducted for the minimization of average temperature/standard deviation. Then the optimal shape of liquid domain is converted into 1D flow routine by thinning algorithm. After that, another topology optimization is performed on the flow channel cross-section plane to get the best cross-section shape of channels. The liquid domain of the final heat sink is then obtained by scanning the optimized flow channel cross-section along the 1 Dimension (1D) flow routine and solving the interference by introducing cylinder joints. Finally, two kinds of twice topology optimized heat sinks including TTOHS-1 with minimized temperature variation as optimal goal and TTOHS-2 with minimized average temperature as optimal goal are generated by combining the liquid domain and a cuboid using Boolean Operation. The performance of heat sinks is numerically investigated, and the results indicate that the thermal performance of TTOHS-1 and TTOHS-2 are much better than that of the traditional heat sink with straight channels (TSCHS). When Re = 689, the average temperature and the maximum temperature of the heat source surface of TTOHS-1 are decreased by 4.99 % and 6.29 % respectively, compared to the TSCHS. The Nusselt number is increased by 46.16 % while the thermal resistance is reduced by 33.13 %. At last, the thermal and flow performance of the TTOHS-1 is studied by conducting experiments, showing that the numerical results agree well with that of the experiment.

Characterisation studies of two front-end electronics chips designed for SiPM readout

A new front-end ASIC named ”PIST” (pico-second timing) has been successfully developed using 55 nm CMOS technology for the silicon photomulplier (SiPM) readout with a single channel with a major aim of fast timing. We performed extensive tests to evaluate the timing performance of a dedicated test stand equipped with a PIST chip. The results show that the system timing resolution can reach sub 10 ps for large SiPM signals, while the PIST intrinsic timing resolution is better than 5 ps. The PIST dynamic range has been further extended using the time-over-threshold (ToT) technique. Meanwhile, we fully characterised a new commercially available SiPM-readout 32-channel ASIC for developments of future high-granularity crystal calorimetry, including the single photon calibration and the dynamic range of different gain regions. Other promising potentials include fast timing resolution, fast readout speed and low power dissipation. Comprehensive measurements were made with a laser beam and high-energy particle beams with crystals and SiPMs. First testing results show that this chip has an excellent signal-to-noise and a large dynamic range. This contribution will introduce the ASICs as well as dedicated test stands and also present highlighted results including the timing resolution, single photon calibration and dynamic range.

Polyurethane/Carbon Nanotube-Based ThermoSense Electronic Skin: Perception to Decision Making Aided by Internet of Things Brain.

Human skin has several receptors collaborating with the brain to provide appropriate "decisions" when applying stimuli. Several research articles state that biomimetic electronic skin (e-skin) is reportedly used for sensor-related applications and performs similarly to natural skin. However, research reporting the capability of the e-skin to make decisions and therefore react upon exposure to adverse conditions is still in its nascent stage. Herein, we report the development of an e-skin, ThermoSense, that can thermoregulate by making appropriate decisions. Thermoplastic polyurethane and multiwalled carbon nanotubes were used as the model composite. The heating and sensing capabilities of the optimized e-skin were studied in detail. In the study window, the e-skin demonstrated excellent electrothermal conversion efficiency by generating a temperature of 192 °C, consuming a power of 2.23 W. A finite element modeling (FEM) was adopted to determine the distribution of the filler in the case of the optimized e-skin and thus was used to probe the reason for the heating across the e-skin via mapping of the internal energy across the sample. FEM results and experimental findings are in strong agreement. Additionally, the e-skin demonstrated its capability to act as a thermal sensor with a 0.947% °C-1 sensitivity. To integrate the decision-making capabilities of the e-skin, an Internet of Things (IoT) brain console was made using the e-skin and electronic chips by leveraging More than Moore's concept. The IoT brain was automated with decision-making programming that was controllable via an in-house-developed mobile application. The console worked exclusively under simulated conditions. When there was a shift from the set point temperature, it started to heat. Postusage, the e-skin matrix was recycled, and the recycled e-skin demonstrated a marginal decrement in performance attributes. This study opens new avenues for developing decision-making e-skins for next-generation human-machine interphases.

Ru Passivation Layer Enables Cu-Cu Direct Bonding at Low Temperatures with Oxidation Inhibition.

Stacking semiconductor chips allows for increased packing density within a given footprint and efficient communication between different functional layers of the chip, leading to higher performance, improved speed, and reduced power consumption. In such vertical stacking, achieving homogeneous electrical and mechanical bonding between heterogeneous chips is crucial, which is termed Cu to Cu direct bonding (CCDB) technology. However, conventional CCDB required a high temperature of over 250 °C to allow Cu diffusion and a vacuum condition for inhibiting Cu oxidation, limiting its practical utilization. Here, we propose that the covering of the Ru layer enables a reliable CCDB as low as 200 °C without concerns regarding oxidation. The bonding strength was as high as 2.24 MPa, and it was endurable at the -45 and 125 °C temperature cycle test for 500 cycles. Through microscopic analysis, we have identified that Cu diffuses through the intercluster boundaries of the Ru layer and moves to the surface, and these atomic Cu ions are recrystallized at the bonding interface, enabling stable bonding at lower temperatures. Specifically, we observed a trade-off between Cu diffusion distance and oxidation inhibition capability depending on the thickness of Ru and found that a 6 nm-thick Ru is optimal, balancing these factors.

Synergistic performance enhancement of lead-acid battery packs at low- and high-temperature conditions using flexible phase change material sheets

Thermal management of lead-acid batteries includes heat dissipation at high-temperature conditions (similar to other batteries) and thermal insulation at low-temperature conditions due to significant performance deterioration. To address this trader-off, this work proposes a thermal management solution based on flexible phase change materials (PCMs) with moderate thermal conductivity and other favourable properties including high specific heat capacity and high latent heat. A novel type of flexible PCM sheets is prepared with paraffin, olefin block copolymers (OBC) and expanded graphite using the co-melting method. The flexible PCM sheets are attached to a common type of lead-acid battery packs (12 Ah, dimensions of 151 × 98 × 97 mm) and thermal management performance is experimentally investigated at –10 °C and 40 °C as low- and high-temperature conditions, respectively, along with 25 °C as a baseline case for comparison purposes. Thermal properties of the battery packs such as temperature regulation and electric properties including charge/discharge capacities and rates are studied synchronously based on a standard high-performance battery detection facility. The results indicate that at –10 °C condition, the PCM sheet enhances thermal insulation of the battery pack and significantly promotes the service temperature during the charging processes. Compared with a benchmark pack attached with an encapsulated sheet, the charge and discharge capacities of the PCM-attached pack are improved by 3.7% and 5.9%, respectively. At 40 °C condition, phase transition of the PCM sheet restrains the temperature rise of the battery pack, with a maximum temperature decrease of 4.2 °C during the charging processes relative to the benchmark pack, and the temperature of the PCM-attached pack is maintained below 45 °C across 60% of the overall charge period. The overcharge and overdischarge have also been alleviated by 3.2% and 2.8%, respectively, and thus the running stability and service lifespan can be improved. The proposed PCM sheets with preferable thermal properties demonstrate potential to promote performance of lead-acid battery packs and such components are also expected to improve heat dissipation and thermal insulation in similar applications including building energy saving, thermal management of electronic chips and thermal regulation of electronic devices.

PhotoSolver: A bidirectional photonic solver for systems of linear equations

Solving systems of linear equations is one of the most fundamental challenges in computing, with ubiquitous applications in science and engineering. Solving large-scale linear equations is particularly challenging, requiring tremendous computing expenses. However, conventional solvers in electronic digital computers face inevitable physical bottlenecks that hinder further advancements in electronic chips. Unlike the electronic architectures, optical computing harnesses the inherent advantages of lights, such as ultimately high speed, negligible energy consumption, and high parallelism, making optical architectures attractive sources for ultra-high speed analog computing. Especially, recent advances in integrated photonic circuits bring exciting new possibilities for high performance computing based on photonic chips. In this work, we propose a bidirectional PhotoSolver using the propagation of optical signals in different directions on a single integrated photonic chip to perform multiple operations in solving systems of linear equations, scalable to solve large-scale systems. Specifically, we propose an in situ approach to iteratively update solutions by performing the forward and backward propagations within a single photonic chip. Furthermore, we propose a partitioning approach to solve large-scale systems using arrays of photonic chips. Numerical experiments demonstrate these capabilities with representative systems of linear equations. By utilizing lights propagating in integrated photonic chips, our PhotoSolvers provide a promising computing architecture to solve large systems of linear equations, with potentials in wide computational applications.

Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications

This article deals with the analysis of irregularly shaped single turn octagonal spiral inductors for millimeter-wave and sub-THz CMOS IC designs. Simulations and experimental results, along with theoretical formulations, are used to characterize these irregular structures. This article proposes a novel approach for efficient use of silicon chip area by reshaping the on-chip inductors used in millimeter wave (mm-wave) applications without compromising the performance of the inductors. Especially in CMOS RFICs when a space constraint exists in either X- or Y-direction in their layout, such reshaping can be attempted. Moreover, two novel methods of reshaping the inductors are proposed and studied thoroughly. The study of these irregular shapes has interesting conclusions, which are validated through on-wafer measurements. Certain methods of reshaping result in inductors which do not have degradation in their quality factors (Q), while other approaches degrade the Q. Based on these insights, a design methodology is proposed for designers who need to reshape their inductors to irregular structures while not compromising on the quality factor. The measurement results agree with the simulations and prove that the proposed reshaping is practically possible.

An integrated coupled oscillator network to solve optimization problems

Solving combinatorial optimization problems is essential in scientific, technological, and engineering applications, but can be very time and energy-consuming using classical algorithms executed on digital processors. Oscillator-based Ising machines offer a promising alternative by exploiting the analog coupling between electrical oscillators to solve such optimization problems more efficiently. Here we present the design and the capabilities of our scalable approach to solve Ising and quadratic unconstrained binary optimization problems. This approach includes routable oscillator connections to simplify the time-consuming embedding of the problem into the oscillator network. Our manufactured silicon chip, featuring 1440 oscillators implemented in a 28 nm technology, demonstrates the ability to solve optimization problems in 950 ns while consuming typically 319 μW per node. A frequency, phase, and delay calibration ensures robustness against manufacturing variations. The system is evaluated with multiple sets of benchmark problems to analyze the sensitivity for parameters such as the coupling strength or frequency.

Integrating resilience and reliability in semiconductor supply chains during disruptions

The semiconductor industry, a cornerstone of modern technology, has been crucial in driving globalization and supporting various sectors, from consumer electronics to automotive industries. However, in recent years, the industry has faced substantial challenges threatening its ability to meet the surging demand for semiconductor chips. Disruptions at any point in the supply chain, from raw material sourcing to end-product delivery, can substantially influence the semiconductor ecosystem. The intricate nature of such SCs makes them highly vulnerable to various disruptions, emphasizing the critical need for building resilient and reliable supply chain strategies. This article presents comprehensive research aimed at addressing critical gaps in the understanding and management of resilience and reliability within the semiconductor supply chain (SSC). This study proposes a multi-objective mixed-integer non-linear programming (MO-MINLP) model to configure an SSC while considering reliability and resilience measures. It emphasizes and draws attention to the importance of resilience and reliability in managing SSC disruptions during a pandemic and potential future epidemic outbreak. Exploring the precise breakdown of batch transportation between two sites shows how disruption can affect product flow along the SC. The applicability of the proposed method is demonstrated through a numerical example of an SSC, solved using the LINGO solver. Finally, a sensitivity analysis is conducted on the model's parameters to assess the capability and effectiveness of the results from managerial viewpoints.

Adjustable temperature and high thermal conductivity composite phase change material based on sodium acetate trihydrate–alanine/expanded graphite for thermal management of electronic devices

Phase change energy storage technology using phase change materials (PCMs) is a viable solution to effectively address the heat dissipation problems of electronic devices. Herein, we proposed to prepare a modified PCM using CH3COONa·3H2O (SAT) as main PCM, 9 wt% DL-Alanine (DL) as temperature modifier, and 2 wt% Na2HPO4·12H2O as nucleating agent. Calculations using density functional theory method confirmed that the adjustment of DL on phase change temperature of SAT was originated from the hydrogen bond between them. Then, the modified PCM was loaded into 14 wt% expanded graphite (EG) to obtain a composite PCM with a suitable phase change temperature of 52.9 °C, phase change enthalpy of 227.4 J/g as well as supercooling degree of 6.6 °C, and the thermal conductivity of the composite PCM was as high as 11.52 W·m−1·K−1. SEM and pore structure analyses showed that the modified PCM was successfully loaded into the pore structure of EG, and their combination was verified by XRD and FT-IR as a physical interaction. After 200 heating–cooling cycles, the phase change temperature and enthalpy of the composite PCM was basically unchanged along with consistent crystal structure and chemical composition, showing an excellent thermal reliability. A comparative analysis applied in a testing system showed that with loading of the composite PCM temperature control module, the critical time of the electronic chip was extended by 4670 s and the thermal equilibrium temperature was decreased by 20.4 °C, presenting a good thermal management performance. Therefore, the prepared composite PCM had great potential for application in thermal management of electronic devices.

Piezoelectric micropump cooler for high-power electronic cooling

Micro-liquid cooling is highly effective for the thermal management of electronic chips. However, it is challenging to apply to high heat flux and compact electronic devices because of the limited cooling power and large pump volume. To address this issue, a compact piezoelectric micropump cooler (PMC) integrating a parallel piezoelectric micropump (PPMP) and a heat sink with a fluid guidance structure is designed. The flow and heat transfer performance of the PMC is theoretically optimized through a numerical coupling model considering mechanics, flow-solid heat transfer, and piezoelectric effect. Simulation results suggest that a copper electrode-PZT ratio of 1.4 increases the output flow rate of the PMC, and the design of five fluid guidance structures enhances its heat dissipation effectiveness. Based on the optimized results, the PMC prototype is manufactured employing 3D printing technology. Experimental results show that the flow rate maximum is 62 mL/min with a precision of 0.07 mL/V·min. When the flow rate of PMC increases to 50 mL/min, the temperature of a heat source with 50 W/cm2 can be reduced to 57 °C, which is comparable with the simulation value. The developed model accurately characterizes the heat transfer properties of the PMC thermal management approach, providing a valuable reference for future research. The proposed PMC is characterized by its compact size, high level of integration, and exceptional cooling performance, making it suitable for electronic cooling applications with high heat flux.

Next Generation Heterogeneous 3D IC Chip Packaging

The demand for a faster and more efficient IC has been steadily increasing more than ever to accommodate the trend of Artificial Intelligence, Industry 4.0, Machine Learning, and Big Data. Traditionally, the semiconductor industry has kept up with demand of faster and more efficient IC by shrinking the size of transistor. As we approach a 1 nm transistor the technological challenge will be challenging to overcome as quantum tunneling becomes more pronounced and would decrease the reliability of the chip. To overcome this technological challenge, an advance packaging of 3D IC chip technology has been developed and delivered to market such as CoWoS (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out). However, the aforementioned technology have their drawbacks with CoWoS uses interposer and TSV (through-silicon substrate via) which make it costly, time consuming, and wastes a lot of energy and InFO is limited in the number of layers it can accommodate for chiplets. Both of those technology are currently limited to 2 or 3 layer of IC and difficult to be modularize. In this study, we aim to develop a heterogeneous 3D IC package that can overcome the aforementioned problem which is modular, cost-effective, able to integrate chip from different manufacturers, and capable to stack more than 3 layers of ICs. This study has successfully completed the first stage of development by employing an advanced package consisting of Epoxy substrate with 200Å Ti/500Å Pt/1000Å Au metal interconnects, previously fabricated as a base for 3D stacking. Keywords : 3D IC Package, Advance Packaging, Modulable IC Packaging, Heterogeneous Integration Figure 1

(Dielectric Science and Technology Division Poster Award, 1st Place) The Influence of Pad Micro-Features on Chemical Mechanical Polishing (CMP) Performance: Insights from Computational Fluid Dynamics (CFD)

With semiconductor chip dimensions shrinking below 7 nanometers, Chemical Mechanical Planarization (CMP) becomes more critical [1], [2]. To meet the increasing demand for precision and uniformity in the fabrication of wafers and chips, enhancements in CMP consumables and operating conditions are necessary. To address these requirements, novel pad designs have been developed, particularly those that do not require conditioning [3]. It is known that the CMP polishing rate depends on pressure, pad wafer relative velocity, and the distribution of pad asperities [4]. As conventional pads provide small and random contact areas, the external pressure applied by the head determines the material removal rate (MRR) [5] Advanced pads with micro-features provide more contact areas and help deliver consistent pressure and slurry distribution during Chemical Mechanical Polishing (CMP) [6], [7]. This study uses computational fluid dynamics (CFD) to simulate the flow between pad and wafer surfaces to determine how pad surface micro-features affect the CMP process. The abrasive residence time, total fluid pressure, and slurry flow velocity are evaluated for four distinct pad micro-feature geometries: square, square-circle, circle, and ellipse. Increasing the number of edges in the pad micro-feature patterns increases pressure drop, leading to more interaction between pad and slurry and enhancement of MRR. The findings of this study confirm the effectiveness of micro-featured pads in optimizing CMP processes and provide valuable insights into the influence of microfeature geometries on critical parameters for improving the semiconductor fabrication process.[1] J. Seo, Journal of Materials Research, 36, 235–257, Jan, 2021.[2] B. Suryadevara, Advances in Chemical Mechanical Planarization (CMP). Woodhead Publishing, 2021.[3] S. Lee and E. Hwang, “Smart pad fabrication for CMP,” LMA Res Rep, vol. 10, pp. 100–104, 2002.[4] G. Ahmadi and X. Xia, J Electrochem Soc, 148, G99, 2001.[5] X. Xia and G. Ahmadi, Particulate Science and Technology, 20, 187–196, 2002.[6] S. Lee, G. Kim, M. Mcgahay, H. Kim, and H. Cho, “Pad Designs-To navigate the fundamentals of CMP.”[7] M. Mcgahay, G. Kim, S. Lee, H. Cho, and H. Kim, “Critical Feature Size of Polishing Pad and Its Performance.”

Numerical Study on the Heat Dissipation Performance of Diamond Microchannels under High Heat Flux Density

Heat dissipation significantly limits semiconductor component performance improvement. Thermal management devices are pivotal for electronic chip heat dissipation, with the enhanced thermal conductivity of materials being crucial for their effectiveness. This study focuses on single-crystal diamond, renowned for its exceptional natural thermal conductivity, investigating diamond microchannels using finite element simulations. Initially, a validated mathematical model for microchannel flow heat transfer was established. Subsequently, the heat dissipation performance of typical microchannel materials was analyzed, highlighting the diamond’s impact. This study also explores diamond microchannel topologies under high-power conditions, revealing unmatched advantages in ultra-high heat flux density dissipation. At 800 W/cm2 and inlet flow rates of 0.4–1 m/s, diamond microchannels exhibit lower maximum temperatures compared to pure copper microchannels by 7.0, 7.2, 7.4, and 7.5 °C, respectively. Rectangular cross-section microchannels demonstrate superior heat dissipation, considering diamond processing costs. The exploration of angular structures with varying parameters shows significant temperature reductions with increasing complexity, such as a 2.4 °C drop at i = 4. The analysis of shape parameter ki indicates optimal heat dissipation performance at ki = 1.1. This research offers crucial insights for developing and optimizing diamond microchannel devices under ultra-high-heat-flux-density conditions, guiding future advancements in thermal management technology.