Silicon Carbide MOSFETs Research Articles

Threshold voltage instability of SiC MOSFETs under very‐high temperature and wide gate bias

AbstractThreshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages.

Short Circuit Protection of Silicon Carbide MOSFETs: Challenges, Methods, and Prospects

Short Circuit Protection of Silicon Carbide MOSFETs: Challenges, Methods, and Prospects

Surge current management in Dynamic Reverse Bias reliability testing of WBG devices for automotive application

Efficient management of high-magnitude current spikes during Dynamic Reverse Bias (DRB) reliability testing is critical for early detection of potential issues such as gate oxide degradation in wide bandgap (WBG) devices. This paper addresses the challenges of DRB testing, particularly focusing on current surges caused by rapid dv/dt switching events in WBG devices. Compliance with AQG-324 guidelines, which require a dv/dt of >50 kV/µs, often results in significant current surges due to parasitic capacitance. These surges can reach tens of amperes, leading to excessive self-heating and potentially damaging sensitive measurement circuitry. This study introduces an innovative method to filter out capacitive displacement current spikes without affecting leakage current, reducing surge intensity by over 100 times and enabling efficient DRB testing of up to 1.5 kV WBG devices. The validation process includes simulating a Wolfspeed Power Silicon Carbide (SiC) MOSFET model in LT-Spice and conducting hardware tests on three different 1.2 kV SiC devices from Wolfspeed, Infineon, and Rohm. An optimized PCB design was employed to minimize circuit parasitics, showing good alignment between simulation and hardware testing outcomes.

Research on anti-single event ability and reinforcement method of SiC MOSFET

Abstract High-voltage silicon carbide (SiC) metal-oxide field-effect transistor (MOSFET) is limited by its ability to resist single event effect (SEE), so it is necessary to study its ability to resist SEE and form an effective reinforcement method. In this paper, it will be studied that how the influence of device structure on the anti-single event ability of SiC MOSFET from the irradiation experiment, and the safe working area of single event leakage degradation of the device is examined. It is found that the width of junction field effect transistor (JFET) and P- type ohmic contact interval both affect the SEE of the device. The SEE mechanism of the device is analyzed based on the experimental results. And the failure caused by local electrothermal stress concentration is confirmed. In view of this mechanism, the reinforced structure is designed with SiO2 barrier layer added in the single event sensitive area, the electrical stress is effectively alleviated, and the peak drain current is reduced by about 18%.

Demonstration of 800°C SiC MOSFETs for Extreme Temperature Applications

Silicon Carbide (SiC) enhancement mode MOS electronics offer several benefits for realizing analog, digital and mixed signal electronics, but limitations on gate dielectric reliability has limited the adoption of MOS in high temperature application. In this work, we report GE’s lateral SiC MOSFETs exceeding previously reported temperature capabilities for SiC MOSFETs with experimental results that have shown that >500°C operation of SiC MOSFETS is possible with >400 hours demonstrated at 620°C, and short-term functionality demonstrated to 800°C. The result shows that MOS-based SiC electronics can continue to be a viable choice for circuit implementations at extreme temperatures >600°C.

Junction temperature monitoring of silicon carbide MOSFET based on turn‐off voltage spike

AbstractBecause of the advantages of high switching speed, silicon carbide (SiC) devices are widely used in high‐power power electronic equipment. Real‐time monitoring of junction temperature is very important for the safe operation of equipment. There have been many studies on traditional junction temperature monitoring methods based on Si IGBT, but the dynamic characteristics of SiC MOSFETs are changed due to their different physical structure and parasitic parameters, which make the traditional methods no longer applicable. In this paper, the junction temperature can be extracted from the switching process of SiC MOSFET by using the turn‐off voltage spike as the index of thermosensitive electrical parameter (TSEP). In addition, the effect of working voltage, current, and different materials on turn‐off voltage spike is also studied. The simulation platform of Ansys/Simplorer and the experimental test platforms are built, and the theory of junction temperature detection based on turn‐off voltage spike is verified. The simulation and experimental results show that turn‐off voltage spike is a feasible TSEP, which can be used to extract junction temperature of SiC MOSFET with good linearity and instantaneity.

Power Cycling Performance of 3.3 kV SiC-MOSFETs and the Impact of the Thermo-Mechanical Stress on Humidity Induced Degradation

Recently, silicon carbide (SiC) power modules of the 3.3 kV voltage class became available and are a promising candidate to replace silicon power modules in traction applications. However, the more than three times higher Young’s Modulus compared to silicon leads to a reduced lifetime under thermo-mechanical stress. This could pose a significant obstacle in their implementation, since traction applications are particularly demanding in their mission profiles with respect to load cycling, but also to environmental conditions. Thus, the thermo-mechanical stress is not just limiting the lifetime itself, but might also promote the humidity induced degradation due to delamination or micro-cracks. In this work, multiple power cycling tests at different temperature swings on 3.3 kV SiC MOSFET chips in a power module were performed, to assess their ruggedness under thermo-mechanical stress. Before or afterwards, these modules were tested under standard HV-H3TRB conditions to verify the interaction between thermo-mechanical and humidity stress on the robustness of the modules.

Optimization Method of SiC MOSFET Switching Trajectory Based on Variable Current Drive

Silicon carbide (SiC) MOSFETs exhibit superior performance compared to traditional silicon (Si) MOSFETs, characterized by faster switching speeds, lower on-resistance, higher breakdown voltage, and greater operational temperature tolerance. These attributes make SiC MOSFETs highly suitable for applications in electric vehicles, charging stations, and mobile devices. However, their rapid switching speed can intensify current and voltage overshoot and oscillations during device switching, leading to increased device losses or potential damage. To address this issue, this paper proposes a current-type active gate drive (AGD) circuit. The circuit first detects the rate of change in the drain current and drain-source voltage. Subsequently, it employs an analog amplifier circuit and adjustable drive resistors to decelerate the rate of change in the drain-source voltage and drain current. As a result, overshoot and oscillation in the drain-source voltage and drain current are mitigated. Experimental results demonstrate that the proposed AGD circuit can reduce drain current overshoot by 60%, drain-source voltage overshoot by 15.38%, and waveform oscillations. Additionally, the AGD circuit decreases conduction and turn-off losses by 24% and effectively mitigates electromagnetic interference (EMI) issues within the frequency range of 0.1 to 3 MHz.

Performance Enhancement in LC Series Resonant Inverters with Current-Controlled Variable-Transformer and Phase Shift for Induction Heating

This article presents an analysis of a converter based on an LC resonant inverter for induction heating applications. It employs a current-controlled variable transformer (VT) in conjunction with phase shift regulation (PS) to operate at a fixed frequency close to the resonance frequency. The converter maintains a small switching angle, enabling substantial load variations without sacrificing zero voltage switching (ZVS) for the transistors. This innovative method enhances the inverter’s performance across the entire operating range. Additionally, a new design of the transformer structure with a variable ratio will be analyzed, enabling mathematical modeling. The obtained results demonstrate a performance exceeding 99%. Both the inverter and variable transformer designs were experimentally validated using a 15 kW, 200 kHz converter for induction heating applications with silicon carbide (SiC) MOSFETs.

Positive Bias Temperature Instability in SiC-Based Power MOSFETs.

This paper investigates the threshold voltage shift (ΔVTH) induced by positive bias temperature instability (PBTI) in silicon carbide (SiC) power MOSFETs. By analyzing ΔVTH under various gate stress voltages (VGstress) at 150 °C, distinct mechanisms are revealed: (i) trapping in the interface and/or border pre-existing defects and (ii) the creation of oxide defects and/or trapping in spatially deeper oxide states with an activation energy of ~80 meV. Notably, the adoption of different characterization methods highlights the distinct roles of these mechanisms. Moreover, the study demonstrates consistent behavior in permanent ΔVTH degradation across VGstress levels using a power law model. Overall, these findings deepen the understanding of PBTI in SiC MOSFETs, providing insights for reliability optimization.

Advanced gate driving concepts and switching optimization for SiC semiconductors

Silicon carbide (SiC) MOSFETS are increasingly favoured in power electronics for their improved properties compared to silicon-based counterparts, such as IGBTs. Their ability to operate at higher switching frequencies and execute faster switching transients is notable. However, these features also raise significant concerns with electromagnetic interference (EMI). To exploit the full capabilities of SiC-based technology, meticulous design strategies encompassing the power stage, commutation loop, and gate drive are essential. This paper conducts a comprehensive review of existing gate drive techniques aimed at enhancing the performance of SiC devices. Moreover, this study introduces an innovative approach for optimizing switching processes through the use of active gate drivers (AGD). By pre-mapping the gate-source voltage profiles for different conditions (such as load current, temperature, and DC-link voltage), it is possible to achieve a significantly improved switching trajectory. This optimization process can be applied on a cycle-by-cycle basis in practical scenarios. Herein, pre-mapping and optimization have been experimentally confirmed in a half-bridge configuration. Through simulation, it is demonstrated that optimizing the switching trajectory can lead to a balanced compromise between EMI and switching losses, showcasing the potential for significant performance enhancements in SiC device operation.

Investigation into active‐gate‐driving performance and potential closed‐loop controller implementations for silicon carbide MOSFET modules

AbstractActive gate driving (AGD) is a promising concept for achieving high‐performance power transistor switching. This is particularly crucial for Silicon Carbide (SiC) MOSFETs since their inherently fast switching characteristics give rise to severe overshoots and oscillations which translate into increased levels of electromagnetic interference (EMI) emissions. In this paper, an AGD strategy using a single‐pulse applied during the switching transient is considered for a 1200 V 400 A SiC MOSFET module. The effect of single‐pulse timing, load current, and temperature on the switching performance is analyzed in detail. The radiated EMI reduction benefits are quantified by H‐field and E‐field probes. A conceptual closed‐loop AGD approach is presented and compared to open‐loop operation. For the transistor turn‐off case under full load current of 400 A, experimental results show that it is possible to reduce voltage overshoot by 43.3%, voltage and current oscillations by 69.7% and 52.2% respectively, and EMI by 76.6%, with a trade‐off in the switching energy by a relatively minor increase of 18.2%, compared to the conventional gate driving case. For the turn‐on case, current overshoot was reduced by 32.7%, EMI by 52%, voltage and current oscillations by 54.6% and 52.8%, respectively, with a penalty of 50.9% increase in the switching loss.

SiC MOSFET Active Gate Drive Circuit Based on Switching Transient Feedback

Due to the influence of parasitic internal parameters and junction capacitance, the silicon carbide (SiC) power devices are frequently marred by significant overshoots in current and voltage, as well as high-frequency oscillations during the switching process. These phenomena can severely compromise the reliability of SiC-based power electronic converters during operation. This study delves into the switching transient of the SiC MOSFET with the goal of establishing a quantitative correlation between the gate driving current and the overshoot in both the drain-source voltage and the drain current. In light of these findings, the innovative active gate drive (AGD) circuit, which features an adjustable gate current, is introduced. Throughout the switching process, the AGD circuit employs a dynamic monitoring and feedback mechanism that is responsive to the gate voltage and rate of change in the drain-source voltage and drain current of the SiC MOSFET. This adjustment enables gate driving current to be actively modified, thereby effectively mitigating the occurrence of overshoots and oscillations. To empirically validate the efficacy of the proposed AGD circuit in curbing voltage and current overshoots and oscillations, a double-pulse experimental setup was meticulously constructed and tested.

Design and validation of a novel semiconductor area optimised 3300 V SiC half bridge for MMC

AbstractThis article presents the design and experimental validation of a novel semiconductor area optimised 3300 V half bridge with Silicon Carbide (SiC) MOSFETs for HVDC converters. Based on a loss simulation, the problem statement is provided. On this results, a mathematical derivation for the optimised semiconductor area design is executed. After this step, a system loss simulation shows the performance in efficiency and specific output power. Finally, a proof of concept was provided by a scaled hardware test setup to characterise the dynamic behaviour of the novel SiC half bridge design compared to the conventional SiC half bridge.

Assessing thermal resistance as a degradation metric for solder bump arrays in discrete SiC MOSFET packages

The development of innovative power electronics solutions for automotive applications introduces new reliability requirements for electronic assemblies and interconnection technologies. Many of the reliability methods used in power electronics require extensive experimental data, resulting in long product design cycles. This work focuses on developing a simulation-driven approach to assess the solder joint reliability of a discrete silicon carbide MOSFET by monitoring its degradation under power cycling in the thermal and thermo-mechanical domains using the thermal resistance of the stack as a failure metric. Active power cycling tests are performed to determine the loading condition at which end-of-life is reached due to a 20% increase in thermal resistance. Numerical analysis using finite element simulations is conducted to gain a physical understanding of the failure criterion, allowing to monitor solder degradation based on the thermal resistance and to pinpoint failure at individual interconnects within a solder bump array. The proposed methodology aims to accelerate the quality assurance and product qualification processes of discrete power electronic devices.

A multi‐objective optimization approach for modeling and analyzing the impact of drive parameters in SiC power converters

SummaryThis paper introduces an equivalent model including the parasitic parameters analysis of silicon carbide (SiC) MOSFETs in order to enhance their performance for high‐power density applications. The model is used to establish a mechanism that evaluates the effect of drive parameters on switching losses and electrical stress of power devices, providing a theoretical basis for optimizing the design of drive parameters. The paper finds the Pareto solution of the multi‐objective optimization model through iterative calculation of design variables, using this mechanism. The methodology is validated through experimental results from an SiC power prototype, showing an efficiency of 98.9% and safe electrical stress levels under 1500 V/100 kW operating conditions.

A Behavior Model of SiC DMOSFET Considering Thermal-Runaway Failures in Short-Circuit and Avalanche Breakdown Faults

Accurate fault simulation and failure prediction have long been challenges for SiC MOSFETs users. This paper presents a behavior model of Silicon Carbide (SiC) double-implanted MOSFET (DMOSFET), considering thermal-runaway failures in short-circuit and avalanche breakdown faults on the basis of cell-level physical processes. The proposed model can simulate the faults with extremely high accuracy and precisely predict SiC DMOSFET’s short-circuit withstand time and critical avalanche energy. By finite-element simulations, cell-level physical processes of short-circuit and avalanche breakdown faults are clarified. The mechanisms of thermal-runaway failures are deeply discussed with references to existing studies. Based on semiconductor and device physics mechanisms, the proposed model is constructed upon a traditional behavior model of SiC MOSFET with several parallel branches that are proposed to describe the thermal-runaway failures during both faults. The Cauer thermal network model is used for estimating junction temperature within it. The proposed model is constructed in Simulink, and it is validated using short-circuit and unclamped inductive switching (UIS) tests.

Applications and challenges of Silicon Carbide (SiC) MOSFET technology in electric vehicle propulsion systems: A review

Silicon Carbide (SiC) MOSFET technology plays a pivotal role in the drive systems of electric vehicles (EVs), offering key applications and facing significant challenges. This paper provides an overview of the fundamental principles and characteristics of SiC MOSFETs, highlighting the unique properties of SiC materials. It delves into the critical applications of SiC MOSFETs in electric vehicle drive systems, including motor drives and inverters, and analyzes the advantages of using SiC MOSFETs for efficient energy conversion at high temperatures. The paper also discusses the key challenges faced by SiC MOSFET technology, such as stability issues under high-temperature environments, avalanche breakdown and tolerance issues affecting power supply reliability, and manufacturing cost and consistency issues that limit widespread application. Innovative solutions to these challenges are explored, including strategies for improving stability under high temperatures, techniques for suppressing avalanche effects and enhancing power supply reliability, and innovations in manufacturing processes to reduce costs and improve consistency. The paper concludes by summarizing the crucial role of SiC MOSFET technology in electric vehicle drive systems, emphasizing the importance of innovative solutions to address its challenges, and looking forward to its continued contribution to technological advancements in the field of electric vehicles.

A python implementation based lattice Boltzmann method for thermal behavior analysis in silicon carbide MOSFET

In the new global industrial sector, electronics systems efficiency has become a central issue should be improved. Recently, there has been renewed interest for addressing this challenge by integrating Silicon Carbide (SiC) technology in industrial systems due to its outstanding materials properties compared to other used material. Meanwhile due to continue minimization of the scale of electronic devices, SiC MOSFETs are highly affected by thermal behavior, a major issue that requires further scientific investigation. In this paper, a Python code-based Lattice Boltzmann Method is implemented to characterize the thermal behavior inside a SiC MOSFETs. The aim of this essay is to explore the relationship between the hotspot and the specularity parameter which is the probability of phonons scattering in the considered nano structure. What emerges from the results reported in this work is that there is an association between the reduction of hotspots inside Silicon Carbide MOSFET and the augmentation of specularity parameter. For Rth−1 = 108 W/(m2K) and specularity parameter of 0.7 and 0.3, the temperature difference was 1.74 K and 1.95 K, respectively while it was 1.21 K and 1.47 K for Rth−1 = 1010 W/(m2K) at the same specularity parameters.

A Simulator for Investigation of Breakdown Characteristics of SiC MOSFETs

Breakdown characteristics play an important role in silicon carbide (SiC) power devices; however, the wide bandgap of SiC poses a challenge for numerical simulation of breakdown characteristics. In this work, a self-developed simulator employing a novel numerical processing method to prevent convergence issues, based on semi-classical transport models and including several kinds of mobility, generation and recombination models, is used to investigate the performance and breakdown characteristics of 4H-SiC MOSFETs in high-power applications. Good agreement between our simulator and an experiment and commercial TCAD was achieved. The simulator has good stability and convergence and can be used as a powerful tool to design and optimize semiconductor devices. Further, the breakdown characteristics are evaluated with different factors, including lattice temperature, device structure and doping profiles. Our results show that the doping profile plays the most important role in the breakdown voltage, followed by the device structure, while the impact of lattice temperature is found to be minimal.