Silicon Carbide Metal-oxide-semiconductor Field-effect Transistors Research Articles

High‐frequency resonant operation of an integrated medium‐voltage SiC MOSFET power module

Industrial processes which use induction and dielectric heating are still relying on resonant converters based on vacuum tubes. New emerging medium-voltage silicon carbide (SiC) semiconductor power devices have a potential to replace vacuum tubes and allow for more efficient and compact converters in the high-frequency range. High-voltage packages have been proposed in the literature that are suitable for the 10 kV SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), and its fast voltage switching capabilities in hard-switched applications have been demonstrated. However, no packaging is presented which allows the high-frequency operation of a 10 kV SiC MOSFET die. This study proposes the design of a power module for MHz resonant operation of a 10 kV SiC MOSFET. At high switching frequencies, the gate losses become substantial, thus the gate driver is included inside the power module package to ensure a low inductive and high thermally conductive design as seen from the gate driver. The inductance of the proposed power module layout structure is evaluated using ANSYS Q3D Extractor. The thermal performance of the integrated gate-driver circuitry is experimentally verified. Finally, the resonant operation of a medium-voltage SiC MOSFET power module is demonstrated experimentally at 1 MHz.

Design and testing of the 40 kV/20A solid-state switch based on SiC MOSFETs for ECRH on J-TEXT Tokamak

Cathode power supply provides high voltage and large energy for electron gyrotron on J-TEXT tokamak. When faults (e.g. internal arc fault) happen on electron gyrotron, the power supply should interrupt within few tens of microseconds. Although the cathode power supply could switch off quickly by itself, frequent failures could decrease the reliability of the power supply without additional protection measures. For the safety of electron cyclotron resonance heating (ECRH) system, solid-state switch is necessary in ECRH protection. A design of a 40 kV/20A solid-state switch was proposed in this paper. To improve the switching performance of the switch, the power devices connecting in series was silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), which replaced traditional solution such as silicon (Si) insulated gate bipolar transistor (IGBT). For the purpose of evaluating and comparing the characteristic of SiC MOSFET and Si IGBT, a dual-pulse test was completed and SiC MOSFET showed the significant advantages. Furthermore, a voltage-clamped snubber circuit was adopted to ensure the voltage balance for each SiC MOSFETs during static and dynamic process. Then, the analysis and validation of the circuit was provided. Finally, the solid-state switch was built and tested by experiment. The results show that the switch works adequately, the switching-off time is 4.7us with 38 kV voltage and 20A current capacity.

Failure Mechanism of Avalanche Condition for 1200-V Double Trench SiC MOSFET

Due to superior properties of silicon carbide (SiC), the unipolar conduction mechanism of metal-oxide-semiconductor-field-effect transistor (MOSFET), and the structural feature, double trench SiC MOSFETs have great potential to be one of the next-generation power switches. In this article, an avalanche safe operation area (SOA) is established, and a new failure behavior of 1200-V double trench SiC MOSFET is revealed timely through unclamped inductive switching (UIS) test (300 K of initial temperature). With comprehensive analyses involving terminal impedance measurement, monitoring of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> before and after each avalanche test, inner electric field comparison by physics-based device modeling, maximum die temperature estimation, and decapsulation validation, the predominant failure mechanism (fracture of trench gate oxide) is identified for double trench SiC MOSFET under UIS test. Before the maximum die temperature approaches the melting point of source metal, the fracture of the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer located at gate trench bottom and corner occurs, which is degraded by duration, excessive electric field, and elevated temperature. Accordingly, we propose I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> as a predicting indicator of avalanche failure, which should be a key monitoring scheme in particular for trench type SiC MOSFET.

A High-Voltage Solid-State Switch Based on Submodule Topology of SiC MOSFETs for J-TEXT Tokamak

Due to safety and reliability concerns, high-voltage solid-state switch is required for electron cyclotron resonance heating system on J-TEXT Tokamak. It cuts off the power supply within a little time usually in microseconds, when a fault occurs. At present, wide-bandgap semiconductors based on silicon carbide (SiC) show superior material properties enabling potential power device operation at higher voltage, current, and switching speeds than current silicon (Si) semiconductors. SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are considered to be a better solution for the basic component of the switch than Si insulated gate bipolar transistors (IGBTs). To solve the problem of voltage balancing in series-connected MOSFETs, a submodule with four, 1.7 kV/40 A rated MOSFETs in series has been developed and experimentally tested. A voltage-clamped snubber circuit is designed to control the overvoltage of each MOSFET. The turn-off performance of the proposed circuit and traditional circuit has been compared by simulation, and the submodule has also been evaluated in a dual-pulse test. Finally, the solid-state switch with 16 submodules in series has been tested by a dummy load. The experimental results show that switch can operate successfully, and the switching performance satisfies the anticipated demand.

A Comparison between Si and SiC MOSFETs

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has developed quickly and become one of the most important devices for a wide range of applications. There is an increasing need for power MOSFET devices with low power consumption and high energy efficiency. Silicon (Si) and Silicon Carbide (SiC) are two kinds of materials used in power MOSFET devices, which have their own advantages of performance for each use. This paper makes a comparison of the on-resistance and high-temperature performance between Si and SiC MOSFETs. The analysis of the differences between the two will mainly come out from the perspective of material properties, and the conclusion of what is the ideal material for power MOSFET devices will be finally drawn.

Magnetic Near-Field Strength Prediction of a Power Module by Measurement-Independent Modeling of Its Structure

This paper presents a simulation scheme based on the S-parameters for simultaneously predicting the circuit operation of a power module (PM) and its consequent magnetic near-field (NF) strength. The PM comprises silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). The circuit simulation is carried out using the S-parameterized PM aided by the SiC MOSFET die model, which allows for a precise replication of the switching waveforms. Note that the S-parameterized process needs no measurement data of the PM. The only experimental data are the characteristics of the specific SiC MOSFET dies used in the PM to adjust the die model. A buck converter is configured with the PM, and the magnetic NF radiated from the PM is measured in order to verify the validity of the proposed scheme. The magnetic field detection probe does not measure the magnetic field itself; instead, it measures the electromotive force (EMF) induced by the magnetic field. Accordingly, the simulated magnetic NF should be converted to the corresponding EMF, which enables a comparison of the measured and simulated results. This simulation scheme works successfully to predict the magnetic NF, but modeling the whole converter system is indispensable.

Analytical and Simulation Fair Comparison of Three Level Si IGBT Based NPC Topologies and Two Level SiC MOSFET Based Topology for High Speed Drives

Wide bandgap (WBG) power devices such as silicon carbide (SiC) can viably supply high speed electrical drives, due to their capability to increase efficiency and reduce the size of the power converters. On the other hand, high frequency operation of the SiC devices emphasizes the effect of parasitics, which generates reflected wave transient overvoltage on motor terminals, reducing the life time and the reliability of electric drives. In this paper, a SiC metal-oxide-semiconductor field-effect transistor (MOSFET) based two level (2L) inverter is systematically studied and compared to the performance of Si insulated-gate bipolar transistor (IGBT) based three level (3L) neutral point clamped (NPC) inverter topologies, for high speed AC motor loads, in terms of efficiency, overvoltages, heat sink design, and cost. A fair comparison was introduced for the first time, having the same output voltage capabilities, output current total harmonic distortion (THD), and overvoltages for the three systems. The analysis indicated the convenience of using the SiC MOSFET based 2L inverter for lower output power. In the case of the maximum output power, the heat sink volume was found to be 20% higher for the 2L SiC based inverter when compared to 3L NPC topologies. Simulations were carried out by realistic dynamic models of power switch modules obtained from the manufacturer’s experimental tests and verified both in the LTspice and PLECS simulation packages.

Comparative Design of Gate Drivers with Short-Circuit Protection Scheme for SiC MOSFET and Si IGBT

Short-circuit faults are the most critical failure mechanism in power converters. Among the various short-circuit protection schemes, desaturation protection is the most mature and widely used solution. Due to the lack of gate driver integrated circuit (IC) with desaturation protection for the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), the conventional insulated gate bipolar transistor (IGBT) driver IC is normally used as these two devices have similar gate structure and driving mechanism. In this work, a gate driver with desaturation protection is designed for the 1.2-kV/30-A SiC MOSFET and silicon (Si) IGBT with the off-the-shelf driver IC. To further limit voltage-overshoot at the rapid turn-off transient, the active clamping circuit is introduced. Based on the experiments of switching characterization and short-circuit test, the SiC MOSFET shows faster switching speed, more serious electromagnetic interference (EMI) issue, lower switching loss (half), and higher short-circuit current (1.6 times) than the Si IGBT, even with a slower gate driver. Thus, a rapid response speed is required for the desaturation protection circuit of SiC MOSFET. Due to the long delay time of the existing desaturation protection scheme, it is technically difficult to design a sub- μ s protection circuit. In this work, an external current source is proposed to charge the blanking capacitor. A short-circuit time of 0.91 μ s is achieved with a reliable protection. Additionally, the peak current is reduced by 22%.

Comparative efficiency analysis for silicon, silicon carbide MOSFETs and IGBT device for DC–DC boost converter

In present study, a comparative efficiency analysis for silicon (Si), silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistor (IGBT) device based DC–DC boost converter is performed. Due to different gate-drive characteristics of power semiconductor devices such as Si, SiC MOSFETs and IGBT device, different voltage levels are required to drive aforementioned devices. A 500 W boost converter for wide input voltage range (30–72 V) and 110 V output voltage is designed having a single gate driver circuit for Si, SiC MOSFETs and IGBT. A single gate driver provides the gate-source (or base-emitter in case of IGBT) signal for all the devices which eliminates the use of separate gate driver circuit. Si MOSFET and IGBT are driven by 12 V gate-source voltage whereas SiC MOSFET is operated by 18 V gate-source voltage using the gate driver circuit. An experimental study is performed for the comparative efficiency analysis for Si, SiC MOSFETs and IGBT device based converter for 20 and 50 kHz switching frequencies. It is found that SiC based converter provides highest efficiency ≈ 97.8%, whereas the lowest efficiency ≈ 94% is found for IGBT based converter at 20 kHz switching frequency. SiC based converter gives higher efficiency because lower conduction loss owning to lower on-state resistance as compared to Si MOSFET. Besides this, SiC application has another advantage such as low switching loss at higher frequency resulting compact size of converter. However, use of IGBT at higher switching frequency results in higher switching losses, hence lower efficiency of the converter.

Fault-Tolerant Inverter Operation Based on Si/SiC Hybrid Switches

The silicon (Si)/silicon carbide (SiC) hybrid switch comprising a Si insulated gate bipolar translator (IGBT) and a SiC metal-oxide-semiconductor field effect transistor (MOSFET) in parallel offers not only excellent performance and cost tradeoff but also inherent switch-level redundancy for potential power converter fault-tolerant operation. It is possible to operate the power converter even when either the SiC MOSFET or the Si IGBT experiences an open-circuit fault. This article first analyzes various switch failure scenarios and then proposes a novel fault-tolerant control strategy for a single-phase inverter based on the Si/SiC hybrid switches to mitigate a single-point switch failure and maintain inverter operation. Experimental results validate the effectiveness of the proposed fault-tolerant control strategy.

A Single Voltage-Balancing Gate Driver Combined With Limiting Snubber Circuits for Series-Connected SiC MOSFETs

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are required to be connected in series to meet the high-voltage requirement since the blocking voltage of a single device is limited. In order to solve the voltage unbalancing problem in such a series-connection application, a single voltage-balancing gate driver combined with limiting Snubber circuits is proposed in this article. This gate driver only requires one standard driver circuit to drive two series-connected SiC MOSFETs by adding simple coupling circuits, and limiting Snubber circuits are applied for voltage balancing, and thus, low-cost, simple structure and high reliability are acquired. The analysis is given to demonstrate the working process of such a circuit structure, and the key parameters’ design and setting are focused on. In the LTspice simulation of two SiC MOSFETs in series, the proposed gate driver shows good voltage balancing performance as the power loop current increasing. Besides, the branch of series-connected SiC MOSFETs is in reliable ON- or OFF-state during steady process. Finally, the experimental results further verify the performance of proposed single voltage-balancing gate driver.

Impact of $RC$ Snubber on Switching Oscillation Damping of SiC MOSFET With Analytical Model

As the most popular wide bandgap (WBG) power device, the silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) has been widely adopted in the power electronics applications and brings in the benefits, including reduced switching losses, enhanced switching frequency, and improved power density. However, the switching oscillation and the electromagnetic interference (EMI) become more serious due to the rapid switching speed of SiC MOSFET. Thus, adding $RC$ snubber branch is considered as an effective method to suppress such unwanted oscillation in the early works. In this article, the switching transient of SiC MOSFET with $RC$ snubber is investigated with an analytical model based on the finite-state machine (FSM). The accuracy of the proposed analytical model can be verified by comparisons between the calculated and measured waveforms during the switching transition. In addition, the impacts of the $RC$ snubber on switching oscillation, switching loss, and high-frequency (HF) EMI noise have been comprehensively investigated based on the model, which shows that the added $RC$ snubber can effectively avoid the switching oscillation and reduce the level of HF EMI without increasing switching loss.

Voltage Balance Switching Scheme for Series-Connected SiC MOSFET LLC Resonant Converter

To achieve high efficiency and power density, silicon carbide (SiC)-based Inductor-Inductor-Capacitor (LLC) resonant converters are applied to the DC/DC converter stage of a solid-state transformer (SST). However, because the input voltage of an SST is higher than the rated voltage of a commercial SiC device, it is essential to connect SiC devices in series. This structure is advantageous in terms of voltage rating, but a parasitic capacitance tolerance between series-connected SiC devices causes voltage imbalance. Such imbalance greatly reduces system stability as it causes overvoltage breakdown of SiC device. Therefore, this paper proposes a switching scheme to solve the voltage imbalance between SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The proposed scheme sequentially turns off series-connected SiC MOSFETs to compensate for the turn-off delays caused by parasitic capacitor tolerances. In addition, dead-time selection methods to achieve voltage balance and zero voltage switching simultaneously are provided in detail. To verify the effectiveness of the proposed scheme, experiments were conducted on a 2 kW series-connected SiC MOSFET LLC resonant converter prototype.

Pressureless Silver Sintering of Silicon-Carbide Power Modules for Electric Vehicles

Pressureless silver (Ag) sintering was optimized at 250°C in vacuum and nitrogen gas atmosphere with silicon carbide (SiC) chips, and silicon nitride active metal-brazed substrates (AMB). A 1200-V/200-A power module was developed using a pressureless Ag-sintered live SiC metal–oxide–semiconductor field-effect transistor (MOSFET) device and a Si3N4 AMB substrate module, and diverse reliability tests were performed. The void content and the bonding layer thickness of the Ag sinter joints were 1.2–3.4% and 68.5 µm. The bonding strength of the Ag sinter joints after thermal cycling testing (TCT) were slightly decreased due to the crack generation. In contrast, high-temperature storage testing (HTST) was carried out for a long time at high temperature, the sintering process occurred continuously, and the shear strength increased by 31% after HTST. The drain–source on-resistance (RDS(ON)) of a SiC MOSFET power module before and after the TCT and power cycle test was similar to the as-sintered state without change.

Evaluation of the V SD ‐method for temperature estimation during power cycling of SiC‐MOSFETs

An accurate temperature estimation is a substantial necessity to evaluate the outcome of a power cycling test. For devices with a forward biased pn-junction in the main current path, there is a well-known and understood method using its forward voltage drop at a small sensing current. Since metal–oxide–semiconductor field-effect transistors (MOSFETs) do not provide a pn-junction in forward mode, this method cannot be applied directly. A similar method to estimate the junction temperature of a MOSFET is the VSD(T)-method, which uses the junction of the reverse body diode. While this method is gaining wide acceptance for junction temperature estimation during power cycling of silicon carbide MOSFETs, no comprehensive investigation on its accuracy, stability and susceptibility towards degradational shift has been performed so far. In this work, the results of an investigation on the VSD(T)-method with an evaluation of its precision and suitability for temperature estimation during power cycling tests of silicon carbide MOSFETs are presented.

Safe Operation of Maximum Temperature for Planar Gate SiC Mosfet under Avalanche Stress Shock

The silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (MOSFET) exhibits its superior dynamic characteristic due to significant shrink of chip size as a result of SiC wide band gap. This advantage transfers to the fast switching speed (i.e., higher dI/dt, dV/dt) of device, promoting high efficient and high power dense applications. When turn-off process, however, the sharp current variation may result in SiC MOSFET suffering avalanche stress. This shock becomes one of reliability issues for SiC MOSFET, influencing the reliability of the converter further. Recently, the avalanche related studies of SiC MOSFET raise extensive investigations and discussions. It is found that the achieved avalanche energy (E av) of a specific SiC MOSFET is varied based on different load in the unclamped inductive switching (UIS) test and the underlying avalanche breakdown cause is relevant to thermal runaway. Therefore, it is of necessity to fully understand the role of temperature in the SiC MOSFET during avalanche mode. Meanwhile, a relatively direct and concise indicator to estimate the avalanche failure of SiC MOSFET is expected in practical scenario, even though various components are entangled inside the subject during avalanche shock. In this paper, avalanche capability of 1200V CREE SiC MOSFET characterizing planar gate structure is assessed using various load (3.6mH, 1.1mH, 0.3mH) UIS and heat induced avalanche failure is analyzed. Through the SiC MOSFET suitable UIS test bench, the withstanding avalanche energy of 1200V rated CREE MOSFET (planar gate) under various avalanche shocks are achieved. Furthermore, verified by the experimentally calibrated TCAD simulation based-on the subject, the underlying mechanism for the avalanche breakdown is revealed. Through the investigation of temperature distribution inside device during UIS process, it confirms that the maximum temperature play predominant role in avalanche damage. When the temperature located at interface of Pbase/N drift region rises up to melting temperature of metal system of source, i.e., around 900K, it results in avalanche catastrophic failure of device. Based on this failure mechanism, accordingly we establish a maximum temperature limit (T av(max)) of SiC MOSFET to guarantee safe operation in terms of avalanche shock. The indicator T av(max) is defined as a critical limit of avalanche damage inside planar gate SiC MOSFET.

Statistical Analysis of the Electrothermal Imbalances of Mismatched Parallel SiC Power MOSFETs

Thanks to the increasing availability of silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) with outstanding static and dynamic performances, the number of applications in which these devices are used is rapidly growing. Despite that, the maximum current rating of such devices is usually limited at few hundred amps, which sets an upper bound for the power level at which these transistors can be adopted. A viable solution to this problem consists in paralleling several SiC MOSFETs. However, the design of parallel configurations needs optimization since mismatched performances can cause the enhanced stress of a subset of devices, which can ultimately lead to premature failure of the whole module. In this contribution, several sets of Monte Carlo (MC) electrothermal simulations of parallel SiC MOSFETs are used to systematically relate the deviations of devices and circuit parameters to the resulting uneven power dissipation. To this purpose, a set of relevant parameters is identified and statistically described. Thereafter, the simulation of a 200-kHz synchronous buck converter relying on mismatched parallel MOSFETs is performed as a case study. Eventually, a methodology to derive a guideline for the design of reliable multichip configurations is developed. The methodology is based on the iteration of MC simulations for different tolerances of the parameters.

Radiation Response of Negative Gate Biased SiC MOSFETs.

Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are expected as power electronic devices for high radiative conditions, including nuclear plants and space. Radiation response of commercial-grade prototype SiC MOSFETs with applying the gate bias is of interest, in terms of installation of the device in robots or sensors working under such radioactive circumstances. Due to gamma-rays irradiation, the threshold voltages (Vth) of samples with un- and negative-biased up to −4.5 V slightly shift toward the negative voltage side. In contrast, the positive bias of 2.25 V shifts Vth more negatively. Positive charge densities trapped in the gate oxide of un- and positive-biased samples increased with increasing dose. However, no significant increase was observed for negative-biased samples of −2.25 and −4.5 V. We calculated characteristic parameters for the accumulation of holes in the gate oxide, σpJp which is defined as the product of current density due to holes generated by irradiation and capture cross section for a hole in a trap, and it is lower for these negative biased samples compared with the unbiased case. Application of appropriate negative gate biases to SiC MOSFETs during irradiation suppresses accumulation of positive charges in the gate oxide and negative shift of Vth, due to irradiation.

A Digital-Controlled SiC-Based Solid State Circuit Breaker with Soft Switch-Off Method for DC Power System

Due to the lower on-state resistance, direct current (DC) solid state circuit breakers (SSCBs) based on silicon-carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) can reduce on-state losses and the investment of the cooling system when compared to breakers based on silicon (Si) MOSFETs. However, SiC MOSFETs, with smaller die area and higher current density, lead to weaker short-circuit ability, shorter short-circuit withstand time and higher protection requirements. To improve the reliability and short-circuit capability of SiC-based DC solid state circuit breakers, the short-circuit fault mechanisms of Si MOSFETs and SiC MOSFETs are revealed. Combined with the desaturation detection (DESAT), a “soft turn-off” short-circuit protection method based on source parasitic inductor is proposed. When the DESAT protection is activated, the “soft turn-off” method can protect the MOSFET against short-circuit and overcurrent. The proposed SSCB, combined with the flexibility of the DSP, has the μs-scale ultrafast response time to overcurrent detection. Finally, the effectiveness of the proposed method is validated by the experimental platform. The method can reduce the voltage stress of the power device, and it can also suppress the short-circuit current.

Design of 400 V Miniature DC Solid State Circuit Breaker with SiC MOSFET.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have the advantages of high-frequency switching capability and the capability to withstand high temperatures, which are suitable for switching devices in a direct current (DC) solid state circuit breaker (SSCB). To guarantee fast and reliable action of a 400 V DC SSCB with SiC MOSFET, circuit design and prototype development were carried out. Taking 400V DC microgrid as research background, firstly, the topology of DC SSCB with SiC MOSFET was introduced. Then, the drive circuit of SiC MOSFET, fault detection circuit, energy absorption circuit, and snubber circuit of the SSCB were designed and analyzed. Lastly, a prototype of the DC SSCB with SiC MOSFET was developed, tested, and compared with the SSCB with Silicon (Si) insulated gate bipolar transistor (IGBT). Experimental results show that the designed circuits of SSCB with SiC MOSFET are valid. Also, the developed miniature DC SSCB with the SiC MOSFET exhibits faster reaction to the fault and can reduce short circuit time and fault current in contrast with the SSCB with Si IGBT. Hence, the proposed SSCB can better meet the requirements of DC microgrid protection.