Safe Operation of Maximum Temperature for Planar Gate SiC Mosfet under Avalanche Stress Shock

Abstract

The silicon carbide (SiC) metal-oxide-semiconductor-field-effect transistors (MOSFET) exhibits its superior dynamic characteristic due to significant shrink of chip size as a result of SiC wide band gap. This advantage transfers to the fast switching speed (i.e., higher dI/dt, dV/dt) of device, promoting high efficient and high power dense applications. When turn-off process, however, the sharp current variation may result in SiC MOSFET suffering avalanche stress. This shock becomes one of reliability issues for SiC MOSFET, influencing the reliability of the converter further. Recently, the avalanche related studies of SiC MOSFET raise extensive investigations and discussions. It is found that the achieved avalanche energy (E av) of a specific SiC MOSFET is varied based on different load in the unclamped inductive switching (UIS) test and the underlying avalanche breakdown cause is relevant to thermal runaway. Therefore, it is of necessity to fully understand the role of temperature in the SiC MOSFET during avalanche mode. Meanwhile, a relatively direct and concise indicator to estimate the avalanche failure of SiC MOSFET is expected in practical scenario, even though various components are entangled inside the subject during avalanche shock. In this paper, avalanche capability of 1200V CREE SiC MOSFET characterizing planar gate structure is assessed using various load (3.6mH, 1.1mH, 0.3mH) UIS and heat induced avalanche failure is analyzed. Through the SiC MOSFET suitable UIS test bench, the withstanding avalanche energy of 1200V rated CREE MOSFET (planar gate) under various avalanche shocks are achieved. Furthermore, verified by the experimentally calibrated TCAD simulation based-on the subject, the underlying mechanism for the avalanche breakdown is revealed. Through the investigation of temperature distribution inside device during UIS process, it confirms that the maximum temperature play predominant role in avalanche damage. When the temperature located at interface of Pbase/N drift region rises up to melting temperature of metal system of source, i.e., around 900K, it results in avalanche catastrophic failure of device. Based on this failure mechanism, accordingly we establish a maximum temperature limit (T av(max)) of SiC MOSFET to guarantee safe operation in terms of avalanche shock. The indicator T av(max) is defined as a critical limit of avalanche damage inside planar gate SiC MOSFET.