Failure Mechanism of Avalanche Condition for 1200-V Double Trench SiC MOSFET

Abstract

Due to superior properties of silicon carbide (SiC), the unipolar conduction mechanism of metal-oxide-semiconductor-field-effect transistor (MOSFET), and the structural feature, double trench SiC MOSFETs have great potential to be one of the next-generation power switches. In this article, an avalanche safe operation area (SOA) is established, and a new failure behavior of 1200-V double trench SiC MOSFET is revealed timely through unclamped inductive switching (UIS) test (300 K of initial temperature). With comprehensive analyses involving terminal impedance measurement, monitoring of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> before and after each avalanche test, inner electric field comparison by physics-based device modeling, maximum die temperature estimation, and decapsulation validation, the predominant failure mechanism (fracture of trench gate oxide) is identified for double trench SiC MOSFET under UIS test. Before the maximum die temperature approaches the melting point of source metal, the fracture of the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer located at gate trench bottom and corner occurs, which is degraded by duration, excessive electric field, and elevated temperature. Accordingly, we propose I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> as a predicting indicator of avalanche failure, which should be a key monitoring scheme in particular for trench type SiC MOSFET.