Silicon Capacitors Research Articles

Epitaxial self-assembly of block copolymers on lithographically defined nanopatterned substrates.

Parallel processes for patterning densely packed nanometre-scale structures are critical for many diverse areas of nanotechnology. Thin films of diblock copolymers can self-assemble into ordered periodic structures at the molecular scale (approximately 5 to 50 nm), and have been used as templates to fabricate quantum dots, nanowires, magnetic storage media, nanopores and silicon capacitors. Unfortunately, perfect periodic domain ordering can only be achieved over micrometre-scale areas at best and defects exist at the edges of grain boundaries. These limitations preclude the use of block-copolymer lithography for many advanced applications. Graphoepitaxy, in-plane electric fields, temperature gradients, and directional solidification have also been demonstrated to induce orientation or long-range order with varying degrees of success. Here we demonstrate the integration of thin films of block copolymer with advanced lithographic techniques to induce epitaxial self-assembly of domains. The resulting patterns are defect-free, are oriented and registered with the underlying substrate and can be created over arbitrarily large areas. These structures are determined by the size and quality of the lithographically defined surface pattern rather than by the inherent limitations of the self-assembly process. Our results illustrate how hybrid strategies to nanofabrication allow for molecular level control in existing manufacturing processes.

Electrical characterization of redox-active molecular monolayers on SiO2 for memory applications

Hybrid silicon capacitors have been successfully fabricated by attaching monolayers of redox-active molecules via self-assembly to ultrathin silicon dioxide layers. Capacitance, conductance, and cyclic voltammetric measurements have been used to characterize these capacitors. The presence of distinct capacitance and conductance peaks associated with oxidation and reduction of the monolayers at low gate voltages indicates discrete electron storage states for these capacitors, suggesting their feasibility in memory devices. The inherent molecular scalability and low-power operation coupled with existing silicon technology support the approach of hybrid molecule-silicon devices as a strong candidate for next generation electronic devices.

Investigation of the Contact Resistance between Ti/TiN and Ru in Metal-1/Plate Contacts of Ruthenium Insulator Silicon Capacitor

The contact resistance between Ti/TiN and a Ru electrode in metal-1/plate contacts of ruthenium insulator silicon (RIS) capacitor is investigated. When physical vapor deposition (PVD) Ti/TiN was used as a barrier metal for the metal contact process, a high contact resistance of more than 5000 Ω/contact was obtained due to the oxidation of Ti by the residual oxygen in Ru electrode. On the other hand, with a plasma enhanced chemical vapor deposition (PECVD) Ti/CVD TiN barrier metal, oxidation of Ti was not observed and subsequently a low contact resistance of 15 Ω/contact was obtained. The absence of Ti oxidation with PECVD Ti/CVD TiN can be explained by the reduction of oxygen in the Ru electrode due to the H2 plasma environment in the PECVD-Ti process.

Investigation of the electrical degradation of a metal–oxide–silicon capacitor by scanning thermal microscopy

A scanning thermal microscope is used to study the temperature distribution on the gate surface of a MOS structure submitted to an electric stress. Over a threshold of stress current intensity, hot spots have been observed and then numbered versus stress conditions. The data analysis shows that the hot spots number depends on injected current and also on the MOS structure degradation history. The temperature map of the gate surface is riddled with hot spots since the sample breakdown. Otherwise, hot spots seem to appear in privileged areas like the gate borders. On the basis of the literature, our observations lead us to conclude that hot spots result of degradations inside the structure.

LPCVD-silicon oxynitride films: low-temperature annealing effects

The electrical properties of silicon oxynitride (SiO x N y ) films on Si deposited by low-pressure chemical vapour deposition have been studied. The effect of annealing on SiO x N y films on the basis of frequency analysis of capacitance–voltage and conductance–voltage characteristics of metal–SiO x N y –silicon capacitors in the frequency range 1–300 kHz was determined. The post-deposition annealing results in a decrease of the concentrations of the positive dielectric charge and defects in the silicon substrate. The nature of the dielectric charges is discussed.

Effects of arsenic concentration profile in gate oxide on electric properties of metal–oxide–silicon devices

The effects of arsenic concentration profiles in gate oxides on the electrical properties of metal–oxide–silicon (MOS) capacitors were investigated. It is found that arsenic in the bulk of gate oxide degrades the electric property of MOS devices, which could be due to the electron traps introduced by arsenic. Interestingly, the electric properties of MOS devices can be improved by an increase in the arsenic concentration at the SiO2/Si interface. This improvement may be attributed to the interfacial strain relaxation and/or the replacement of nonbridging bonds. The arsenic concentration profile in gate oxide plays a crucial role for the electric properties of MOS devices.

Capacitance-Voltage Characterization of LPCVD-Silicon Oxynitride Films

LPCVD-silicon oxynitride films with different compositions were deposited on n-Si(111) substrates by reacting dichlorosilane (SiH 2 Cl 2 ) with nitrous oxide (N 2 O) and ammonia (NH 3 ) at a temperature of 860 °C varying the gas flow rate ratio of N 2 O and NH 3 . The electrical properties of the SiO x N y films were studied by analysis of the 1 MHz capacitance-voltage characteristics of the metal-SiO x N y -silicon capacitors. It has been found that with increasing amount of N 2 O in the deposition ambient the concentration of the dielectric charges in the SiO x N y /Si structures goes through a minimum, while the interface trap density gradually decreases. The nature of the defects is discussed.

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.

12.2: A Conformable Electronic Ink Display using a Foil‐Based a‐Si TFT Array

AbstractWe have fabricated prototype lightweight electronic ink displays on a conformable active‐matrix array sheet. The active matrix arrays were built using amorphous silicon thin film transistors and capacitors on a stainless steel foil substrate. These prototype displays possess a resolution of 40 dpi, with 52×64 pixels (active area 1.3 inch × 1.6 inch) on a 1.8 inch × 2.0 inch stainless steel substrate. The display possesses an ink on paper appearance, with wide‐viewing angle and good contrast ratio.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Atomic Layer Deposition- and Chemical Vapor Deposition-TiN Top Electrode Optimization for the Reliability of Ta2O5 and Al2O3 Metal Insulator Silicon Capacitor for 0.13 µm Technology and Beyond

TiCl4-based atomic layer deposition (ALD)- and chemical vapor deposition (CVD)-TiN films are applied as the metal top electrode for Ta2O5 and Al2O3 metal insulator silicon (MIS) capacitor. The effects of factors such as Cl content, step coverage, deposition temperature of the TiN top electrode processes and pre-NH3 flushing on the electrical properties and reliability of the Ta2O5 and Al2O3 MIS capacitor are studied. Among these factors, poor step coverage shows distinctly degraded electrical properties of MIS capacitor, and high deposition temperature of TiN processes also degraded electrical properties, particularly those of Ta2O5. Although similar capacitance and leakage characteristics are measured with high chlorine content and pre-NH3 flushing TiN processes, a difference in the orders of magnitude is observed in time dependent dielectric breakdown (TDDB) measurements. Regarding the deposition temperature and pre-NH3 flushing effect, the electrical and TDDB characteristics of Ta2O5 degrade even more severely than those of Al2O3. Degradation of TDDB in TiN films with NH3 flushing prior to deposition is attributed to the reduction effect of the dielectric material by NH3 gas. Based on the X-ray photoelectron spectroscopy (XPS) analysis results, Al2O3 is chemically more inert than Ta2O5. In addition, the degradation of TDDB characteristics is directly correlated to the early generation of Vp-dependent solid “0” fail bit counts. Due to the relatively low deposition temperature as well as to the excellent step coverage and low resistivity, the ALD-TiN process is ideal for enhancing the reliability of a MIS capacitor.

Extraction of the oxide thickness using a MOS structure quantum model for SiO 2 oxide

In this paper, we present a full quantum model of metal oxide semiconductor capacitance based on a self-consistent resolution of Schrödinger and Poisson equations. The model is used in accumulation to extract the oxide thickness of N + polycrystalline silicon–SiO 2–P silicon capacitors in the range 2–5 nm. The extraction results are in agreement with reference ellipsometric measurements to <±4%. We also show the necessity of a quantum computation of the gate capacitance for high substrate doping and low oxide thickness. The influence of the tunneling current is also discussed.

Electric bidirectional stress effects on metal–oxide–silicon capacitors

Bidirectional electron injections were performed in thick and thin oxides of metal–oxide–silicon capacitors under a constant oxide electric field. Results show that dissymmetry, due to electron trapping near both oxide interfaces, is accentuated when the oxide is thin. However electron trapping is more marked when oxide is thick. Two kinds of thick oxide were used: wet and dry technologies. Wet oxide contains relatively more defects than dry. This is due to hydrogen incorporation in wet oxide during the oxidation process. But this difference is not well marked, because boron atoms injected after the oxidation process would deactivate hydrogen atoms. We describe the electron trapping by a well-known power law. The exponent of this law depends on oxide field polarity and also on oxide thickness but is technology independent. Results also show a nonexpecting behavior of tunneling current during bidirectional stress at a constant voltage. Here, we describe its causes and effects.

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP/sup TMI/) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

Positive charge instability during bidirectional stress on metal–oxide–silicon capacitors

Bidirectional electron injections are made on metal–oxide–silicon capacitors under constant currents or constant voltages. It is shown that both stresses reveal the same generation mechanism of oxide defects and consequently confirm that the gate/oxide interface is more stress resistant than the oxide/silicon interface. It is also shown that the created positive charge is unstable during bidirectional stress. We characterize this instability by studying dielectric defect neutralization following a new procedure. Oxide field intensity and polarity are considered as the principal precursors of this instability. Without any applied field, the neutralization follows a logarithmic law; while under a nonstressing field it follows an exponential law. Both kinetic laws are linked, since the logarithmic law describes the saturation value of the exponential one, and hence both describe the same process. Results of both current and voltage stresses give a power law between the oxide field near the cathode during stress and the capture cross section measured from neutralization kinetics.

Charge separation technique for metal–oxide–silicon capacitors in the presence of hydrogen deactivated dopants

An improved charge separation technique for metal–oxide–silicon (MOS) capacitors is presented which accounts for the deactivation of substrate dopants by hydrogen at elevated irradiation temperatures or small irradiation biases. Using high-frequency capacitance–voltage measurements, radiation-induced inversion voltage shifts are separated into components due to oxide trapped charge, interface traps, and deactivated dopants, where the latter is computed from a reduction in Si capacitance. In the limit of no radiation-induced dopant deactivation, this approach reduces to the standard midgap charge separation technique used widely for the analysis of room-temperature irradiations. The technique is demonstrated on a p-type MOS capacitor irradiated with Co60 γ rays at 100 °C and zero bias, where the dopant deactivation is significant.

Random telegraphic signals in rapid thermal annealed silicon–silicon oxide system

Random telegraphic signals (RTS) have been observed in large-area aluminium–silicon oxide–silicon capacitors, rapid thermal annealed (RTA) in argon at 600–700°C for 50 s. The noise spectra of these devices at higher biases showed a Lorenztian spectrum between 30–400 Hz. We suggested that the RTA process has produced weak spots in the devices. The filling and emptying process of a trap near the weak spot modulates the barrier height and resulted in the RTS and Lorentzian spectrum observed in these devices.

The Properties of Mfmos and MFOS Capacitors with High K Gate Oxides for one Transistor Memory Applications

AbstractMFMOS and MFOS (M: Metal, F: Ferroelectrics, O: Oxide, S: Silicon) capacitors with high k gate oxides, such as ZrO2, HfO2 thin films, have been fabricated for one transistor memory applications. Experimental results showed that ZrO2 and HfO2 have no serious reaction or diffusion into silicon substrate. Due to their high dielectric constant, the operation voltages of MFMOS capacitors are reduced. The MFMOS capacitor exhibits 2V memory window. For lead germanium oxide (PGO) on ZrO2 and PGO on HfO2 MFOS memory cells the memory windows are 1.8 V and 1.6 V, respectively, which are large enough for one-transistor memory applications. The basic mechanism for one-transistor memory applications was also discussed.

Biochemical sensors with structured and porous silicon capacitors

Chemical sensors with structured and porous semiconductor/insulator capacitors have been developed. The sensors have been prepared using standard techniques of semiconductor processing, i.e. by means of an anisotropic and anodic etching process, respectively. Both sensor types exhibit a high, near-Nernstian pH sensitivity of about 54 mV per pH decade. Due to the enlargement of the active sensor area, the measured capacitance values increase up to a factor of 30. These structured and porous electrolyte–insulator–semiconductor (EIS) sensor substrates are suitable as transducer material for biosensors which has been demonstrated by depositing the enzyme penicillinase through physical adsorption onto the respective pH-sensitive EIS capacitors.

Relaxation of positive charge during bidirectional electric stress on metal–oxide–silicon capacitors

Relaxation phenomena of positive charges, created in a metal–oxide–silicon capacitor by bidirectional Fowler–Nordheim electron injections under constant current, have been studied and their kinetics have been quantitatively characterized. After creation, positive charges are neutralized under electron injections at constant current. The gate bias shift caused by the neutralization process has an exponential dependence on time during relaxation irrespective of stress field polarity and stress duration. Analysis of data assuming nonelectron detrapping gives capture cross section values in the range of 3.5–6.7×10−16 to 2.1×10−15 cm2. The compilation of data given in literature and our present results shows that the main responsible defect in the oxide is the amphoteric traps negatively charged near the cathode and positively charged near the anode.