Active Silicon Layer Research Articles

Suppressing the parasitic bipolar action of SOI-MOSFETs by using back-side bias-temperature treatment

The improvements in the device characteristics of fully depleted nMOSFETs/SIMOX treated using a back-side bias-temperature treatment are presented This method suppresses the parasitic bipolar action without causing degradation of device characteristics. Suppression of parasitic bipolar action increases the source-drain breakdown voltage by about 500 mV and increases device lifetime under hot-carrier stress by a factor of 15. The effects of this treatment can be attributed to the generation of traps at the interface between the buried oxide and the active silicon layer.

Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers

Dielectrically isolated substrates containing buried highly conducting WSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 μm thick with a buried WSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 μs were measured indicating the suitability of these substrates for use in device manufacture.

In-Situ Fabrication of Gate Oxide and Poly-Si Film by XeCl Excimer Laser Annealing

We have proposed a new method to form the gate oxide and recrystallize the polycrystalline silicon (poly-Si) active layer simultaneously. During the irradiation of excimer laser, the poly-Si film is recrystallized while the oxygen ion impurities, which are injected into the amorphous silicon (a-Si) film, are activated by laser energy and react with silicon atoms to form SiO2. Our experimental results show that a high quality oxide, a poly-Si film with fine grain, and a smooth and clean interface between oxide and poly-Si film have been successfully obtained by the proposed fabrication method. The maximum oxide breakdown electric field which exceeds 7 MV/cm is obtained.

Laser induced implanted oxide (Ll2Ox) and polycrystalline silicon film simultaneously fabricated by excimer laser irradiation

A method to form the gate oxide and recrystallize the polycrystalline silicon (poly-Si) active layer simultaneously is proposed. During the irradiation of excimer laser, the poly-Si film is recrystallized while the oxygen ion impurities injected into the amorphous silicon (a-Si) film are activated by laser energy and react with silicon atoms to form SiO2. Our experimental results show that a high quality oxide and a poly-Si film with fine grain have been fabricated successfully by the proposed method. High quality interface between oxide and poly-Si films has also been obtained.

Influence Of Silicon Defects On The Electrical Behavior Of Semiconductor Power Devices

AbstractSince power devices require a thick electrically active n-type silicon layer with high resistivity and a large area, their electrical characteristics are extremely sensitive to contamination. If heavy metals diffuse into the silicon wafers during the high-temperature steps, an uncontrolled increase in the leakage current and the on-state voltage can be observed. Furthermore, current filamentation and instabilities of the electrical data can occur. It turned out that the optimization of the cleaning processes, high-temperature steps and gettering treatments alone is not sufficient to avoid such effects. It is also important to avoid silicon crystal defects by proper processing. A dramatic increase in the leakage current was correlated with the appearance of silicon defects decorated with heavy metals. As a consequence of the low doping level of the n-base, the blocking voltage and the failure rate due to cosmic radiation are sensitive to contaminating atoms acting as donors.

Critical Technologies for Poly-Si TFT in High Resolution AM-LCD

ABSTRACTPolycrystalline silicon (p-Si) TFT offers higher aperture ratio with integrated driver circuits compared to the conventional a-Si TFT in AM-LCD application. The advantages of the p-Si TFT as the pixel switching element will be more pronounced for AM-LCDs with large number of scan lines and/or high pixel density. This paper reviews challenges and issues associated with the technology of p-Si TFT, particularly in active silicon layer deposition, solid phase and laser crystallization, hydrogenation, leakage current, performance of different device architectures and reliability. Critical issues affecting the p-Si TFT AMLCD pixel design are analyzed, including: lithographic resolution and overlay accuracy, pixel density and aspect ratio, display format, storage to LC capacitance ratio, and gate dielectric thickness. Predictions on the regimes of dominance for different flat-panel technologies by advantages in performance and-or cost with respect to panel size and pixel density will be presented.

Study on titanium salicide process for thin-film SOI devices

TFSOI (Thin-Film Silicon-On-Insulator) technology has made significant progress recently. In this work, the titanium SALICIDE (Self-Aligned siLICIDE) process has been studied, optimized and applied on a CMOS-compatible TFSOI technology for low-voltage, low-power microwave applications. The gate sheet resistance and total source/drain series resistance of a TFSOI NMOSFET with a 80 nm thick active silicon layer are 6.2 Ω/square and 700 Ω.μm, respectively, with a 30 nm thick titanium disilicide on both the gate and source/drain areas. The maximum oscillation frequency, f max, of a 0.75 μm TFSOI NMOSFET fabricated with this technology is equal to 11 GHz for a supply voltage of 0.9 V.

96/06250 The role of pilot projects and public acceptance in developing wireless power transmission as an enabling technology for space solar power systems

This paper presents a new solar-cell structure obtained by the front-surface texturization of multicrystalline silicon substrate by laboratory technology and main equipments used in characterization of such devices. The structure consists of an antireflection coating, a silicon active layer, front and back wafer contacts. The main objective was the minimizing the production cost maintaining the device performances. For these reasons the general technology cycle consists of maximum seven steps, a multicrystalline silicon substrate was used, the doping profile was optimized by simulations, the front-surface solar cell was texturized in order to reduce the light reflectivity and the wafer back-side was p+-diffused in order to get low series resistance. The performed measurements were in good agreement with simulations and expected results.

Advanced, Thin, Polycrystalline Silicon-Film™ Solar Cells on Low-Cost Substrates

AbstractThin, polycrystalline silicon solar cells have the potential for the realization of a 15%, lowcost photovoltaic product. As a photovoltaic material, polycrystalline material is abundant, benign, and electrically stable. The thin-film polycrystalline silicon solar cell design achieves high efficiency by incorporating techniques to enhance optical absorption, ensure electrical confinement, and minimize bulk recombination currents. AstroPower's approach to a thin-film polycrystalline silicon solar cell technology is based on the Silicon-Film™ process, a continuous sheet manufacturing process for the growth of thin films of polycrystalline silicon on low-cost substrates. A new barrier layer and substrate have been developed for advanced solar cell designs. External gettering with phosphorus has been employed to effect significant improvements leading to effective minority carrier diffusion lengths greater than 250 micrometers in the active silicon layer. Light trapping has been observed in 60-micrometer thick films of silicon grown on the new barrier-coated substrate. An efficiency of 12.2% in a 0.659 cm2 solar cell has been achieved with the advanced structure.

Bulk silicon microelectromechanical devices fabricated from commercial bonded and etched-back silicon-on-insulator substrates

Abstract In this work a new and simple technology for the fabrication of bulk silicon microelectromechanical devices is presented. The microstructures are defined in the silicon active layer of commercially available bonded and etched-back silicon-on-insulator (BESOI) substrates by a single photolithographic step and anisotropic dry etching. The thickness of the structures is only limited by the performance of the dry-etching process. In this work a thickness of 20 μm is used. Various devices have been fabricated, including electrostatic micromotors, microturbines and electrostatically actuated microrelays. An interesting feature of this technology is that the use of BESOI substrates allows the integration of electronic circuits on the substrate used to fabricate the microelectromechanical devices.

Biased-voltage controlled thinning for bonded silicon-on-insulator wafers

A novel method for the preparation of bonded and etch-back silicon-on-insulator is presented and demonstrated in which the surface of the to be thinned silicon wafer near the oxide is biased to inversion, so the bulk of this silicon wafer can be removed by anodic etching using the depletion layer as an etch stop. The high etching selectivity between the bulk silicon wafer and the depletion layer makes it possible to produce a micron/submicron-thick active silicon layer with good thickness uniformity across a 3 in. silicon-on-insulator wafer.

Polycrystalline silicon‐film™ solar cells: Present and future

AbstractFuture crystalline silicon solar cells will have increased performance and reduced cost. Increased performance will come from thin silicon with light trapping, provided that it includes back‐surface passivation. Cost reduction will come from the growth of this thin silicon light‐trapping structure on a low‐cost substrate. the silicon will be polycrystalline. Solar cells formed with thin (&lt; 50 μm) silicon active layers can produce higher conversion efficiencies at reduced material requirements than conventional ingot‐based silicon devices. This paper presents the essential features of high‐performance device design based on thin silicon layers, the design features of the Silicon‐Film−TM technology, the sequence of products that emerge from its development and recent results from the first commercial‐scale, large‐area (225 cm−2) Silicon‐Film−TM solar cell product.

Capacitance studies of the a-Si TFT input stage

Capacitance studies of large area structures which mimic the overlap region between source and gate at the input of an amorphous silicon thin film transistor are used to investigate the nature and distribution of the localised states found within the gate insulator and at the interface between insulator and active amorphous silicon layer.

Thin Polycrystalline Silicon Solar Cells

Solar cells formed with thin silicon active layers (&lt;100 μm thick) offer advantages over thick ingot-based devices. The advantages come in two forms: the first is the potential for higher conversion efficiency than that of conventional thick devices, and the second is a reduction in material requirements. The use of thin polycrystalline silicon for solar cells offers the potential of capturing the high performance of crystalline silicon while achieving the potential low cost of thin films. Experimental and theoretical studies initially uncovered the issues of grain size and thickness as limiting factors. Subsequent work added the issue of back-surface passivation. This article addresses the conditions required for the successful development of polycrystalline silicon into a high efficiency, low-cost, terrestrial product.

0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer

A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- and p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have been realized. High parasitic resistance in the source and drain regions of the 0.1- mu m-gate CMOS/SIMOX tends to increase the propagation delay time. However, 0.1- mu m-gate CMOS/SIMOX devices with a delay time as low as 10 ps can be obtained by reducing the parasitic resistance. >

Suppression of oxidation stacking faults in silicon separation by oxygen

Oxidation of the silicon overlayer in silicon separated by oxygen (SIMOX) is expected to create oxidation stacking faults (OSFs) since this process generates silicon interstitials in the active silicon layer. In spite of this process, recent results reveal that the density of OSFs is very low. A plausible mechanism which can explain the absence of OSFs in SIMOX is that silicon interstitials which are rejected from the silicon overlayer and SiO 2 interface react with SiO 2 of the buried layer to form SiO molecules ( Si + SiO 2 = 2SiO ). These species can diffuse four orders of magnitude faster than silicon through the SiO 2 buried layer to the back interface where they are recombined by the reverse reaction owing to the absence of silicon interstitial supersaturation in this side.

From substrate to VLSI: investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena

A silicon-on-insulator (SOI) technology with a hardened variant is presented, focusing on some of the weak points that could impede the progress of SOI toward the production of high-speed hardened VLSI. The devices described here use the LOCOS isolation method instead of the commonly used MESA and a thin active silicon layer on which no epitaxy takes place. Dose and dose rate tests were performed on both technologies and on various circuits and special-purpose devices. An analysis of the sensitivity of the circuits to single-event upset, (SEU) was made, and a hardness limitation coming from an ion-induced transient caused by substrate-related phenomena was found. Dose, dose rate, and SEU behavior are related to the structural characteristics mentioned above. >