Significant Electron Trapping Research Articles

Study on the single-event burnout mechanism of GaN MMIC power amplifiers

In this Letter, a single-event burnout (SEB) mechanism in gallium nitride (GaN) microwave monolithic integrated circuit power amplifiers with a high linear energy transfer of 78.1 MeV·cm2/mg has been investigated in detail. A typical SEB phenomenon was observed. With the aid of photon emission measurements and scanning electron microscopy, it is found that catastrophic burnout occurs in the power-stage GaN high electron mobility transistors (HEMTs) and the metal–insulator–metal (MIM) capacitors, respectively. For the GaN HEMT, the incident heavy ions will generate electron–hole pairs within it, which can gain enough energy with the transverse high electric field. The high-energy electrons will collide with the lattice near the drain electrode and induce significant electron trapping, which will result in a significant longitudinal local electric field. When a critical electric field is achieved, catastrophic burnout occurs. For the MIM capacitor, the burnout is attributed to the single-event dielectric rupture via severe impact ionization or latent tracks when heavy ions strike it.

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (-2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

Unraveling the Dynamics of Charge Trapping and De-Trapping in Ferroelectric FETs

In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n-channel ferroelectric field-effect transistors (nFeFETs) and pFeFETs. It is discovered that: 1) the degree of charge trapping depends on the substrate that nFeFETs exhibit significant electron trapping but negligible hole trapping during memory write while pFeFETs exhibit much less electron trapping but significant hole trapping when heavily stressed; 2) due to enhanced electric field in the interlayer and semiconductor, the like initial polarization states (i.e., initialized by a pulse of the same polarity as the write pulse) could exacerbate charge trapping induced by the write pulse; 3) electron trapping is fully recoverable while hole trapping shows a semi-permanent component which involves interface trap generation; and 4) less significant charge trapping in pFeFETs allows immediate read-after-write at normal operating conditions.

Air‐ and Active Hydrogen‐Induced Electron Trapping and Operational Instability in n‐Type Polymer Field‐Effect Transistors

Organic field‐effect transistors (OFETs) have attracted much attention for the next‐generation electronics. Despite of the rapid developments of OFETs, operational stability is a big challenge for their commercial applications. Moreover, the actual mechanism behind the degradation of electron transport is still poorly understood. Here, the electrical characteristics of poly{[N,N‐9‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,59‐(2,29‐bithiophene)} (P(NDI2OD‐T2)) thin‐film transistors (TFTs) as a function of semiconductor/dielectric interfacial property and environment are systematically investigated, in particular, how the copresence of water, oxygen, and active hydrogen on the surface of dielectric leads to a sharp drop‐off in threshold voltage. Evidence is found that an acid–base neutralization reaction occurring at the interface, as a combined effect of the chemical instability of dielectrics and the electrochemical instability of organic semiconductors, contributes to the significant electron trapping on the interface of P(NDI2OD‐T2) TFTs. Two strategies, increasing the intrinsic electrochemical stability of semiconductor and decreasing the chemical reactivity of gate dielectric, are demonstrated to effectively suppress the reaction and thus improve the operational stability of n‐type OFETs. The results provide an alternative degradation pathway to better understand the charge transport instability in n‐type OFETs, which is advantageous to construct high‐performance OFETs with long‐term stability.

NARROWBAND GYROSYNCHROTRON BURSTS: PROBING ELECTRON ACCELERATION IN SOLAR FLARES

ABSTRACT Recently, in a few case studies we demonstrated that gyrosynchrotron microwave emission can be detected directly from the acceleration region when the trapped electron component is insignificant. For the statistical study reported here, we have identified events with steep (narrowband) microwave spectra that do not show a significant trapped component and, at the same time, show evidence of source uniformity, which simplifies the data analysis greatly. Initially, we identified a subset of more than 20 radio bursts with such narrow spectra, having low- and high-frequency spectral indices larger than three in absolute value. A steep low-frequency spectrum implies that the emission is nonthermal (for optically thick thermal emission, the spectral index cannot be steeper than two), and the source is reasonably dense and uniform. A steep high-frequency spectrum implies that no significant electron trapping occurs, otherwise a progressive spectral flattening would be observed. Roughly half of these radio bursts have RHESSI data, which allow for detailed, joint diagnostics of the source parameters and evolution. Based on an analysis of radio-to-X-ray spatial relationships, timing, and spectral fits, we conclude that the microwave emission in these narrowband bursts originates directly from the acceleration regions, which have a relatively strong magnetic field, high density, and low temperature. In contrast, the thermal X-ray emission comes from a distinct loop with a smaller magnetic field, lower density, but higher temperature. Therefore, these flares likely occurred due to interaction between two (or more) magnetic loops.

Atom-resolved imaging of ordered defect superstructures at individual grain boundaries

The ability to resolve spatially and identify chemically atoms in defects would greatly advance our understanding of the correlation between structure and property in materials. This is particularly important in polycrystalline materials, in which the grain boundaries have profound implications for the properties and applications of the final material. However, such atomic resolution is still extremely difficult to achieve, partly because grain boundaries are effective sinks for atomic defects and impurities, which may drive structural transformation of grain boundaries and consequently modify material properties. Regardless of the origin of these sinks, the interplay between defects and grain boundaries complicates our efforts to pinpoint the exact sites and chemistries of the entities present in the defective regions, thereby limiting our understanding of how specific defects mediate property changes. Here we show that the combination of advanced electron microscopy, spectroscopy and first-principles calculations can provide three-dimensional images of complex, multicomponent grain boundaries with both atomic resolution and chemical sensitivity. The high resolution of these techniques allows us to demonstrate that even for magnesium oxide, which has a simple rock-salt structure, grain boundaries can accommodate complex ordered defect superstructures that induce significant electron trapping in the bandgap of the oxide. These results offer insights into interactions between defects and grain boundaries in ceramics and demonstrate that atomic-scale analysis of complex multicomponent structures in materials is now becoming possible.

Interfacial transition regions at germanium/Hf oxide based dielectric interfaces: Qualitative differences between non-crystalline Hf Si oxynitride and nanocrystalline HfO 2 gate stacks

The contribution from a relatively low-K SiON ( K ∼ 6) interfacial transition region (ITR) between Si and transition metal high-K gate dielectrics such as nanocrystalline HfO 2 ( K ∼ 20), and non-crystalline Hf Si oxynitride ( K ∼ 10–12) places a significant limitation on equivalent oxide thickness (EOT) scaling. This limitation is equally significant for metal-oxide-semiconductor capacitors and field effect transistors, MOSCAPs and MOSFETs, respectively, fabricated on Ge substrates. This article uses a novel remote plasma processing approach to remove native Ge ITRs and bond transition metal gate dielectrics directly onto crystalline Ge substrates. Proceeding in this way we identify (i) the source of significant electron trapping at interfaces between Ge and Ge native oxide, nitride and oxynitride ITRs, and (ii) a methodology for eliminating native oxide, or nitride IRTs on Ge, and achieving direct contact between nanocrystalline HfO 2 and non-crystalline high Si 3N 4 content Hf Si oxynitride alloys, and crystalline Ge substrates. We then combine spectroscopic studies, theory and modeling with electrical measurements to demonstrate the relative performance of qualitatively different nanocrystalline and non-crystalline gate dielectrics for MOS Ge test devices.

Elimination of GeO 2 and Ge 3N 4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

The contribution from relatively low -K SiON interfacial transition regions (ITRs) between Si and transition metal (TM) gate dielectrics places a significant limitation on equivalent oxide thickness (EOT) scaling for Si complementary metal-oxide-semiconductor (CMOS) devices. This limitation is equally significant and limiting for Ge CMOS devices. Low-K Ge-based ITRs in Ge devices have also been shown to limit performance and reliability, particular for n-MOS field effect transistors. This article identifies the source of significant electron trapping at interfaces between n-Ge or inverted p-Ge, and Ge oxide, nitride and oxynitride ITRs. This is shown to be an interfacial band alignment issue in which native Ge ITRs have conduction band offset energies smaller than those of TM dielectrics, and trap electrons for negative Ge substrate bias. This article also describes a novel remote plasma processing approach for effectively eliminating any significant native Ge ITRs and using a plasma-processing/annealing process sequence for bonding TM gate dielectrics directly to the Ge substrate surface.

Charge Trapping at Deep States in Hf–Silicate Based High- κ Gate Dielectrics

We have observed charge trapping during constant voltage stress in Hf-based high-κ dielectrics at deep traps as well as at the shallow traps. and leakage current dependence on these deep traps further suggest that trapping at deep levels inhibits fast recovery. The earlier findings where charge trapping seemed to be very transient due to the presence of a large number of shallow traps and trapped charge could be eliminated by applying a reverse direction electric field may no longer be valid. The experimentally observed trap energy levels from low-temperature measurements establish a relationship between the origin of the deep traps and their dependence on O vacancy formation in Hf–silicate-based films. Substrate hot electron injection gives rise to significant electron trapping and slow post-stress recovery under negative bias conditions, which confirms that O-vacancy-induced deep defects determine the transient behavior in Hf–silicate-based high-κ gate dielectrics. It is further shown that negative-U transition to deep defects is responsible for trap-assisted tunneling under substrate injection. A fraction of the injected electrons remains trapped at the deep defects and gives rise to significant . This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-κ gate dielectrics.

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.

Ultra-Short Pulse Current–Voltage Characterization of the Intrinsic Characteristics of High-κ Devices

An ultra-short pulse current–voltage (I–V) measurement technique has been applied to high-κ gate transistors to investigate the effects of fast transient charging. It is shown that the fast electron trapping may contribute to the degradation of transistor performance (i.e., low mobility) observed with direct current (DC) characterization methods, as well as pulse techniques in the tens of microseconds range and above. In particular, in the samples with significant electron trapping, the drain current in the saturation regime is shown to improve by up to 40% from its DC values when the characterization is performed with pulse I–V measurements in the nanosecond range.

Nature and location of interface traps in RF LDMOS due to hot carriers

In this paper, the nature and location of hot carrier induced defects is studied for N-channel LDMOS (Laterally Diffused MOS) transistors. These devices are used in wireless base stations and typically operate under high drain bias of 25–30 V, making them highly susceptible to hot carrier injection. In this work, the improvement in hot carrier induced degradation by means of a dummy gate is presented. Using the charge pumping technique, it is demonstrated that, (1) significant electron trapping in the LDD region occurs for devices without a dummy gate in contrast to devices with a dummy gate. (2) For devices with a dummy gate interface traps are preferentially generated in the LDD region.

Charge trapping in thin gate oxides of NMOSFETs at 77K during uniform Fowler-Nordheim electron injection

In this work, charge trapping in thin gate oxides of NMOSFETs at 77K during uniform F–N electron injection is investigated and compared with the situation at 295K. Due to the presence of a large number of neutral deep-level electron traps in gate oxide edges, produced during drain/source formation, significant electron trapping at 77K is detected in this region. In the gate oxide above the bulk channel on the other hand, net positive charges are trapped at 77K in contrast to the net negative charges at 295K. It is found that the enhanced electron trapping (or the more trappy property of gate edges) cannot only reduce device drive current but also significantly degrade device turn-o characteristics.

Charge Trapping in Dielectrics Grown on Polycrystalline Silicon

Significant electron trapping has been observed in thermally grown interlevel oxide on polycrystalline silicon (poly‐Si) structure. The trapped charges were concentrated about 50Å away from the interface between the underlying poly‐Si and the oxide grown upon it. The mechanism responsible for the high density of electron traps appears to be out‐diffusion of phosphorus from poly‐Si. Much less charge trapping was observed when poly‐Si was covered by thermal oxide plus a layer of silicon nitride. The dual dielectric structure also displayed a higher oxide breakdown field strength.

Lateral distribution of hot-carrier-induced interface traps in MOSFETs

The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Electron trapping in SiO2—An injection mode dependent phenomenon

Electron trapping in metal-oxide-silicon structures and its dependence on the injected electron energy distribution and oxide field were studied. It is found that at high injection levels trapping efficiency and saturation level increase with the accelerating field in the Si, and decrease with increase in the oxide field. These results differ markedly from those obtained in low level injection, in which it is assumed that trapping is of electrons injected from the Si into the oxide conduction band. Based on the high level injection experimental results, it is proposed that significant electron trapping is obtained through direct tunneling of hot electrons with energy less than the potential barrier, into localized states in the oxide near the Si-SiO2 interface.

Study of Ionizing Radiation Damage in MOS Structures Using Internal Photoemission

The effects of ionizing radiation in large-geometry MOS structures were studied by use of internal photoemission techniques. Barrier heights at both the silicon-silicon dioxide and the silicon dioxide-metal (chromium and aluminum) interfaces were measured before and after irradiation in a Co60 gamma cell. It was determined that the measured barrier energy heights may be considerably reduced by radiation-induced oxide charge. The internal photoemission technique also provided significant information concerning the effects of impurities in the oxide and the related radiation hardness of the oxide layer. Oxide layers doped with chromium ions showed significant electron trapping at two discrete energy levels (3.4 and 3.8 eV). Samples exhibiting the 3.4 eV level showed great radiation hardness, while those with only the 3.8 eV peak were very radiation soft. The information obtained, using the internal photoemission technique, has provided considerable insight into the mechanisms and fabrication processes associated with radiation-hardened MOS devices.