Signed-digit Number Research Articles

Parallel optical computing using recoded trinary signed-digit numbers

We propose a simple recoded trinary signed-digit number representation for parallel optical computing. This technique performs multidigit carry-free addition and borrow-free subtraction in constant time, using only 50% of the, minterms required in the most recently reported trinary signed-digit arithmetic technique. One may use a single-step optoelectronic or a two step all-optical architecture to implement the proposed technique.

Symmetrically recoded modified signed-digit optical addition and subtraction

Symmetrically recoded modified signed-digit number algorithms are proposed for carry-free arithmetic. The superiority of the new algorithms is established over all other two-step-based symbolic-substitution optical implementations.

Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor

Addition is the most primitive arithmetic operation in digital computation. Other arithmetic operations such as subtraction, multiplication, and division can all be performed by addition together with some logic operations. With the binary number system, addition speed is inevitably limited by the carry-propagation schemes. On the other hand, carry-free addition is possible when the modified signed-digit (MSD) number representation is used. We propose a novel optoelectronic scheme to handle the parallel MSD addition and subtraction operations. An optoelectronic shared content-addressable memroy is introduced. The shared content-addressable memory uses free-space optical processing to handle the large amount of parallel memory access operations and uses electronics to postprocess and derive logic decisions. We analyze the accuracy that the required optical hardware can deliver by using a statistical cross-talk-rate model that we propose. We also evaluate other important device and system performanceparameters, such as the memory capacity or the maximum number of parallel bits the adder can handle in terms of a given cross-talk rate at a certain repetition rate, the corresponding diffraction-limited memory density, and the system's power efficiency. To confirm the underlining operational principles of the proposed optoelectronic shared content-addressable-memory MSD adder, we design and perform initial experiments for handling 8-bit MSD number addition and subtraction and present the results.

Multiplication of signed-digit numbers

A recently proposed technique for common-multiplicand multiplication of binary numbers is shown to be applicable to signed-digit numbers. The authors prove that multiplication of a single k-bit multiplicand by nk-bit multipliers can be performed using 0.306nk additions for canonically recoded signed-digit numbers, whereas the binary case requires 0.375nk additions.

Symbolic substitution modified signed-digit optical adder

A high-accuracy fixed-point optical adder that operates in parallel on many long words and that uses a pipelined correlator architecture is described. A symbolic substitution algorithm with the modified signed-digit number representation is used to perform fixed-point additions with limited carries. A new set of substitution rules and encodings is developed to combine the recognition and substitution steps into one correlation operation. This reduces hardware requirements, improves throughput by reducing the space-bandwidth product needed, and reduces latency (the delay between when data enter the processor and when the final output is available) by a factor of 2. This algorithm and our new modified signed-digit encodings and substitution rules improve the performance of other correlator and noncorrelator optical numeric computing architectures.

High-accuracy pipelined iterative-tree optical multiplication

A high-accuracy optical multiplier that uses an optical correlator is described. A symbolic substitution adder that uses the modified signed-digit number representation is used as the basic module. Emphasis is placed on the multiplication of many long words in parallel with minimum latency. The encoding method we employ in the adders permits the use of a new optical algorithm and architecture to generate partial products in symbolic form in parallel. Our multiplication algorithm and architecture are shown to be preferable to other optical techniques and to be competitive with digital technology; they are also shown to be particularly attractive for matrix-vector multiplication applications.

Efficient trinary signed-digit symbolic arithmetic

A new technique for high-speed trinary signed-digit (TSD) arithmetic that uses optical symbolic substitution is presented. This technique performs multibit carry-free addition and borrow-free subtraction in constant time. The proposed TSD scheme utilizes the minimum number of minterms compared with the previously reported modified signed-digit and TSD number systems.

Decomposition of logic networks with emphasis on signed digit arithmetic systems

This paper describes an attempt to combine advantages of the signed digit number representation, applied at the word-level, and the residue number system applied at the digit-level, to achieve arithmetic decomposition of high-radix systems. Also introduced is a new decomposition algorithm for multiple-output Boolean functions based on partition products. Analysis of the proposed new method of arithmetic decomposition, when compared to an approach based on the theory of digit sets, reveals a more efficient use of data storage plus a higher degree of structural uniformity. The practical importance of the proposed method has been tested on a number of designs for the field programmable gate arrays. Comparison with a commercially available CAD system indicates a significant reduction in implementation complexity

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

A novel hybrid number representation is proposed. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hybrid signed digit logarithmic number system processor

A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. The hybrid SD/LNS processor exploits the parallelism that is offered by the SD number system to boost the performance of the fast LNS processors, and compares favourably to conventional LNS processor designs.

New redundant representations of complex numbers and vectors

The authors present a redundant representation for complex numbers called polygonal representation. This representation enables fast carry-free addition, in a way quite similar to the carry-free addition in signed-digit number systems and is convenient for multiplication. The technique is generalized in order to handle n-dimensional vectors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the implementation of arithmetic support functions for generalized signed-digit number systems

Ordinary signed-digit (OSD) number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha . . .,-1,0,1. . ., alpha ), where alpha is an arbitrary integer in the range r/2 0 and beta >0) explicitly. Zero detection, sign detection, and overflow handling are also treated in depth. >

A novel Josephson adder without carry propagation delay

The authors describe a novel Josephson adder based on the radix-2 signed-digit number representation. In the proposed adder, the addition operation can be carried out in a constant time independent of word length owing to the elimination of the carry propagation chain. A critical path for generating the sum signal can be completed through only three series gates. A carry signal and an intermediate sum signal for all digits in the adder are simultaneously generated in the first step, and the final sum signal is obtained in the second step. Features of the proposed adder are a simple construction, ultra-high speed, and low power consumption. The principle of constructing the adder with an 8 b word length using superconducting quantum interference devices (SQUIDs) is described in detail, and simulation results are presented. Results show that reliable operation can be achieved for the longest delay time of 120 ps for the 8 b adder.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modified signed-digit optical processors using computer-generated holograms

Modified signed-digit (MSD) numbers offer convenient parallel addition and subtraction of bits. The parallel addition of any two MSD numbers, no matter what the values of their bits may be, requires only three bit-pattern transformations. To perform such transformations optically, however, MSD data must be represented in a form suitable for cascade connection. Proposed here is a new cascade-connective MSD optical processor. Adding principles are successfully demonstrated by using an optical threshold device array in addition to new computer-generated holograms that are adjusted to equalize the intensity of their diffracted light beams.

Efficient implementation of regular parallel adders for binary signed digit number representations

Signed digit number representations diminish the latency of addition at moderate hardware cost and thus can play an important role in processor design, especially for processor architectures like superscalar, superpipelining, and VLIW. Moreover, they are very useful for the construction of on-line arithmetic systems that operate in most significant digit first style. Due to inadequate formal models, implementations of adders for signed digit number representations have been somewhat clumsy in the past. Usually it had been overlooked that the choice of a good representation for the digits is of crucial importance to an efficient implementation. In this paper we propose a formal model for addition on binary signed digit number representations that comprises all aspects of representing the digits by bits. We characterize all feasible adder functions, derive lower bounds on the fan-in of time-optimal adder cells for the various representations, and show thereby that there are ‘good’ and ‘bad’ representations.

Very-high-speed VLSI 2s-complement multiplier using signed binary digits

A high-speed 8*8-bit multiplier design for 2s-complement binary numbers is presented. The multiplier uses the binary signed-digit number system to achieve both high speed and layout simplicity, and is implemented in double layer metal 2 mu m CMOS technology. The multiplication time for the array was found by simulation to be 18 ns at 25 degrees C and its size was measured as 1.7 mm*2.3 mm (excluding pads). Power dissipation was calculated as just less than 40 mW at 55 MHz, and the transistor count is 3754 transistors.

Radix-2 SRT division algorithm with simple quotient digit selection

A new and fast algorithm for SRT division that combines a modified version of the Svoboda algorithm with the radix-2 signed-digit number system is presented. The quotient bit selection is a simple function of the two most significant digits of the current partial remainder, and the two operands are each prescaled by a single subtraction.

Fast digit-parallel conversion of signed digit into conventional representations

A new method for conversion from signed digit (SD) to conventional signed-magnitude (SM), radix complement, or diminished radix complement representations is presented. For conversion of an n-digit input, sign detection of n SD numbers called ‘partial’ SD numbers is performed first. Then, the digits of the conventional representation can be generated in parallel. Conversion from radix-2 SD representation to SM representation is presented, as a means of illustrating the method. The proposed method is faster and has a more regular circuit design than the conventional one.

High-speed multiplier for digital signal processing

A high-speed optical system capable of performing <i>n</i>-bit multiplication in a time proportional to log₂<i>n</i> is presented. The simultaneous generation and the optical regrouping of all the partial products and the pairwise addition of the partial products by means of a binary tree of adders capable of adding any two numbers in a single stage (by completely eliminating the carry propagation chain) are unique features of this multiplier. The input data to the multiplier can be in either a binary or a modified signed digit number system. The simultaneous generation and the pairwise addition of the partial products are accomplished by means of the principle of symbolic substitution logic that was originally proposed by Brenner.

Conversion from signed-digit to radix complement representation

A technique for converting a redundant signed-digit number into conventional radix complement form is presented. The converter hardware consists of borrow-look-back and decrementer units which can easily be implemented as combinational circuits. The conversion scheme also offers an easy solution for determining the sign of the signed-digit number.