Signed-digit Number Research Articles

Trinary optical logic processors using shadow casting with polarized light

The tristate logic using signed digit numbers can be used for carry- and borrow-free mathematical operation. This paper deals with the basic logic system using trinary states as well as its implementation using shadow casting technique.

Fast multiplier design using redundant signed-digit numbers

A high speed multiplier design is presented using redundant binary signed-digit number representation internally while the input operands and the output product are in two's complement form. The design of a carry free redundant binary signed-digit (RBSD) adder cell is presented. The multiplication algorithm uses bit-pair recording to generate the partial products. The partial products are added in the form of a binary tree using carry free RBSD adder cells. The regular structure of these adder cells results in a multiplier design that is suitable for VLSI implementation. The increased speed is achieved through the carry free addition of partial products using redundant signed-digit numbers. The use of a recoding scheme will reduce the number of rows of partial products by a factor of two. The proposed multiplier design has a multiplication time of order O(log2 n) and area-time complexity of order O(n2 log2 n) for a word length of n.

Parallel Computing of Modified Signed-Digit Addition and Subtraction Using a Hybrid Optical Computing System Constructed of PROM Devices

An encoding method for optical implementation of addition and subtraction in the modified signed-digit number system is proposed. Parallel computing of the addition is demonstrated by the use of a hybrid optical computing system constructed of PROM devices and electronic circuits.

Radix-16 signed-digit division

A two-stage algorithm for fixed point, radix-16 signed-digit division is presented. The algorithm uses two limited precision radix-4 quotient digit selection stages to produce the full radix-16 quotient digit. The algorithm requires a two-digit estimate of the (initial) partial remainder and a three-digit estimate of the divisor to correctly select each successive quotient digit. The normalization of redundant signed-digit numbers requires accommodation of some fuzziness at one end of the range of numeric values that are considered normalized. A set of general equations for determining the ranges of normalized signed-digit numbers is derived. Another set of general equations for determining the precisions of estimates of the divisor and dividend are derived. These two sets of equations permit design tradeoff analyses to be made with respect to the complexity of the model division. The specific case of a two-stage radix-16 signed-digit division is presented. The staged division algorithm used can be extended to other radices as long as the signed-digital number representation used has certain properties. >

Generalized signed-digit number systems: a unifying framework for redundant number representations

Signed-digit (SD) number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha , . . ., -1, 0, 1, . . ., alpha ), where alpha is an arbitrary integer in the range 1/2r< alpha <r. Such number representation systems possess sufficient redundancy to allow for the annihilation of carry or borrow chains and hence result in fast propagation-free addition and subtraction. The author refers to the above as ordinary SD number systems and defines generalized SD number systems which contain them as a special symmetric subclass. It is shown that the generalization not only provides a unified view of all redundant number systems which have proven useful in practice (including stored-carry and stored-borrowed systems), but also leads to new number systems not examined before. Examples of such new number systems are stored-carry-or-borrow systems, stored-double-carry systems, and certain redundant decimal representations.<<ETX>>

Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems

VLSI-oriented multiple-valued current-mode MOS arithmetic circuits using radix-2 signed-digit number representations are proposed. A prototype adder chip is implemented with 10- mu m CMOS technology to confirm the principle of operation. A multiplication scheme using four-input current-mode wired summations for realizing a high-speed small-size multiplier is presented. The 32*32-b multiplier is composed of 18800 transistors and required fewer interconnections. The multiply time is estimated to be 45 ns by SPICE simulation in 2- mu m CMOS technology. It is shown that the technology is also potentially effective for the reduction of the data-bus area in VLSI. >

Optical systems for digit-serial computation

Optical systems and algorithms are presented for implementing digit-serial (or on-line) computations. These systems achieve high accuracy without the need for A-Ds and incorporate parallelism and carry-free addition to achieve high processing speed. On-line arithmetic allows parallel calculations to be performed by concurrent execution of operations. (Consecutive operations can start before all digits of the previous operations are available.) The algorithms are problem- and step-invariant and inherently allow variable precision as we show. To achieve parallelism, we introduce the modified signed-digit number representation into these algorithms and architectures. This results in new arithmetic rules (new addition rules, a different number of bits needed, a different number of cycles required) from those in conventional digital digit-serial systems. We include sufficient detail (not readily available elsewhere) needed for the design of the units we include. New architectures using optical bistable devices and optical interconnects are described that can implement digit-serial addition, subtraction, multiplication, and division algorithms in this new approach.

Bi‐directional current‐mode basic circuits for the multilevel signed‐digit arithmetic and their evaluation

AbstractFor highly parallel operation, use of a radix‐4 signed‐digit (SD) number system is attractive. Since the SD number system uses more than three values in each digit, multivalued coding is suitable for the implementation of the high‐speed compact arithmetic integrated circuits. We have already proposed the basic idea of multivalued bidirectional current‐mode circuits which are essentially suitable for the SD arithmetic implementation. This paper describes the experimental results of the basic SD arithmetic integrated circuits by means of the bidirectional current‐mode circuits and their evaluation. A parallel SD adder is implemented with 2‐μm CMOS technology and the addition time is estimated to be about 10 ns. The addition time of the SD adder is 14 times faster than that of the conventional ripple‐carry adder and is three times faster than that of the block carry lookahead adder.

New coding scheme for addition and subtraction using the modified signed-digit number representation in optical computation

On propose dans cet article une combinaison diverse d'operations de nombres, a la fois binaires et ternaires, pour la soustraction et l'addition en calcul optique

A 32*32-bit multiplier using multiple-valued MOS current-mode circuits

A 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32*32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2*5.2 mm/sup 2/, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported. >

Carry-free addition of recoded binary signed-digit numbers

Signed-digital number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha ,...,-1,0,1,..., alpha ), where alpha is an arbitrary integer in the range r/2 >

Design of VLSI‐oriented radix‐4 signed‐digit arithmetic circuits using multiple‐valued logic

AbstractRadix‐4 signed‐digit (SD) arithmetic circuits using multiple‐valued logic are proposed from the viewpoint of VLSI implementation. Because of the property of sign‐symmetry in the SD number representation, a new bi‐directional current‐mode MOS technology is employed very effectively in implementing very fast and compact SD arithmetic circuits. These basic operations are simulated and evaluated using SPICE2. Finally, it is demonstrated that these arithmetic circuits can be fabricated using 2 um CMOS technology. For example, a multiply time of 40 ns can be achieved in the SD multiplier with a 17 × 16 bit precision.

A systolic SBNR adaptive signal processor

A new realization for adaptive signal processing units is proposed which uses a special subset of signed digit number representations (SDNR's). This signed binary number representation (SBNR) captures all of the efficiencies of SDNR arithmetic but also makes circuit realizations less complex. Furthermore, a natural interface between analog and digital numbers is provided. The serial on-line processing nature of SBNR utilizes the MSB first. An area/time complexity for VLSI implementations in comparable systolic array architectures contrasts the effectiveness of five different primitive VLSI cells and organizations.

A systolic SBNR adaptive signal processor

A new realization for adaptive signal processing units is proposed which uses a special subset of signed-digit number representations (SDNRs). This signed binary number representation (SBNR) captures all of the efficiencies of SDNR arithmetic and, in addition makes circuit realizations less complex. Furthermore, a natural interface between analog and digital numbers is provided. The serial online processing nature of SBNR utilizes the MSB first. An area/time complexity for VLSI implementations in comparable systolic array architectures contrasts the effectiveness of five different primitive VLSI cells and organizations.

Photonic Computing Using The Modified Signed-Digit Number Representation

Improving the precision of optically performed computations is a critical aspect of photonic computing. One possible method for improving precision is through the use of modified signed-digit (MSD) arithmetic. Optical implementation of MSD arithmetic offers several important advantages over other optical techniques such as the digital multiplication by analog convolution (DMAC) algorithm or the use of residue arithmetic. These advantages include the parallel pipeline flow of digits due to carry-free addition and subtraction, fixed-point as well as floating-point capability, and the potential for performing divisions. We present a brief description of the modified signed-digit number system and suggest one optical architecture for implementing MSD fixed-point addition, subtraction, and multiplication.

On Range-Transformation Techniques for Division

This note points out the close relationship between some of the recently described division techniques, in which the divisor is transformed to a range close to unity. A brief theoretical analysis is presented which examines the choice of quotient digit when this type of division technique is used for conventional and signed-digit number systems.

A Division Algorithm for Signed-Digit Arithmetic

Abstract—The application of a fast division algorithm, particu-larly suitable for floating-point arithmetic, to signed-digit number systems is described. This method, based on the method of A. Svo-boda, is performed in two steps: 1) the divisor is adjusted to be of the form (1+e) where e is a fractional quantity, while the dividend is adjusted accordingly, and 2) the generation of each quotient digit is determined by only one digit in the partial remainder together with the transfer digit (or carry/borrow) emanating from it. A working example of radix 16 is given.

Arithmetic microsystems for the synthesis of function generators

The continuing reduction of the size and cost of integrated circuit logic elements encourages the utilization of more complex logic nets in digital computers. In arithmetic processors, the application of integrated circuits will permit the replacement of sequential logic nets by their combinational equivalents, and the replacement of programmed subroutines by arithmetic fraction generators. At the present time, such function generators are used in the Variable Structure Computer at the University of California, Los Angeles. The potentially low cost of logic elements can be realized if large numbers of elements are contained in one package with a limited number of connections to the outside, and if very few types of packages are used in large quantities. Present-day arithmetic processors cannot be readily subdivided into uniform packages because of irregularities in their internal structure. The paper describes the advantages gained by the application of signed-digit number systems in the design of such packages, called arithmetic microsystems. Three types of combinational microsystems are described and their internal design is illustrated by examples for a radix 16 system. The microsystems can accept conventional binary or signed-digit operands. Combinational reconversion of results to the binary system is also discussed. The application of microsystems is illustrated by radix 16 combinational arrays for the operations of multiplication and division.

Arithmetic microsystems for the synthesis of function generators

The continuing reduction of the size and cost of integrated circuit logic elements encourages the utilization of more complex logic nets in digital computers. In arithmetic processors, the application of integrated circuits will permit the replacement of sequential logic nets by their combinational equivalents, and the replacement of programmed subroutines by arithmetic fraction generators. At the present time, such function generators are used in the Variable Structure Computer at the University of California, Los Angeles. The potentially low cost of logic elements can be realized if large numbers of elements are contained in one package with a limited number of connections to the outside, and if very few types of packages are used in large quantities. Present-day arithmetic processors cannot be readily subdivided into uniform packages because of irregularities in their internal structure. The paper describes the advantages gained by the application of signed-digit number systems in the design of such packages, called arithmetic microsystems. Three types of combinational microsystems are described and their internal design is illustrated by examples for a radix 16 system. The microsystems can accept conventional binary or signed-digit operands. Combinational reconversion of results to the binary system is also discussed. The application of microsystems is illustrated by radix 16 combinational arrays for the operations of multiplication and division.

Signed-Digit Numbe Representations for Fast Parallel Arithmetic

This paper describes a class of number representations which are called signed-digit representations. Signed-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers. Carry-propagation chains are eliminated by the use of redundant representations for the operands. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum (or difference) digit is the function only of the digits in two adjacent digital positions of the operands. The addition time for signed-digit numbers of any length is equal to the addition time for two digits. The paper discusses the properties of signed-digit representations and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff. A brief discussion of logical design problems for a signed-digit adder concludes the presentation.