Efficient implementation of regular parallel adders for binary signed digit number representations

Abstract

Signed digit number representations diminish the latency of addition at moderate hardware cost and thus can play an important role in processor design, especially for processor architectures like superscalar, superpipelining, and VLIW. Moreover, they are very useful for the construction of on-line arithmetic systems that operate in most significant digit first style. Due to inadequate formal models, implementations of adders for signed digit number representations have been somewhat clumsy in the past. Usually it had been overlooked that the choice of a good representation for the digits is of crucial importance to an efficient implementation. In this paper we propose a formal model for addition on binary signed digit number representations that comprises all aspects of representing the digits by bits. We characterize all feasible adder functions, derive lower bounds on the fan-in of time-optimal adder cells for the various representations, and show thereby that there are ‘good’ and ‘bad’ representations.