Signed-digit Number Research Articles

Avoiding intersections of given size in finite affine spaces AG(n,2)

We study the set of intersection sizes of a k-dimensional affine subspace and a point set of size m∈[0,2n] of the n-dimensional binary affine space AG(n,2). Following the theme of Erdős, Füredi, Rothschild and T. Sós, we partially determine which local densities in k-dimensional affine subspaces are unavoidable in all m-element point sets in the n-dimensional affine space.We also show constructions of point sets for which the intersection sizes with k-dimensional affine subspaces take values from a set of a small size compared to 2k. These are built up from affine subspaces and so-called subspace evasive sets. Meanwhile, we improve the best known upper bounds on subspace evasive sets and apply results concerning the canonical signed-digit (CSD) representation of numbers.Keywords: unavoidable, affine subspaces, evasive sets, random methods, canonical signed-digit number system.

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

QCA-Based Adder for Redundant Binary Signed Digit Numbers

QCA-Based Adder for Redundant Binary Signed Digit Numbers

Implementation three-step algorithm based on signed digit number system by using neural network

The need for a simple and effective system that works with high efficiency features such as high processing speed, the ability to solve problems by learning method and accomplish the largest amount of data processing accurately and in little time produces that system, which attracted the efforts of the researcher to employ neural networks in computing away from the complexities that burden traditional computers. We presented a model for the design of the arithmetic circuit for the process of addition the sign digit numbers in a new way to deal with the arithmetic operations, which employment of the use of neural networks, this model includes a theoretical and practical simulation of them. The model relied on the implementation of the addition process based on a three-step algorithm adopted by the signed systems. Which is characterized by the possibility of execution in a parallel way, and therefore it provides the advantage of completion of arithmetic operation regardless of the length of their operands, or in other words, whatever the number of bits in the operands. The simulation of the model is done by entering operands for 6 addition operations (each one has operands are 15-bit length) to be executed simultaneously.

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles

Coordinate rotation digital computer (CORDIC) is widely used in digital signal processing (DSP) to calculate functions. One of the elegant ways to accelerate CORDIC is employment of the redundant binary signed-digit (BSD) number systems, so-called BSD-CORDIC. This paper aims to achieve efficient BSD-CORDIC structures for generic/specific initial angles. First, three generic BSD-CORDIC algorithms are optimized by exploiting a suitable data gating technique as well as appropriate BSD encodings. The synthesis results demonstrate that for generic CORDIC, the proposed BSD-CORDIC schemes enhance the existing ones in terms of speed, power consumption, and area overhead. Second, the look-ahead BSD-CORDIC is proposed as a special case of BSD-CORDIC with specific initial angles. We also show that for the applications like fast Fourier transform (FFT), where the initial angles are known in advance, the proposed look-ahead BSD-CORDIC with the posibit-negabit encoding, as our best presenting structure, noticeably improves speed, power consumption, and area overhead.

VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.

Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA

Abstract Now a day’s speed is very important to meet the requirement of user in today’s chips. We want faster smart phones, laptops and other gadgets that can work at a speed even beyond our imagination. In this paper we have designed a fast multiplier which can provide better results. RBSD stands for Redundant Binary Signed Digit number system which enables fast computing by reducing carry propagation time as carry is not propagated to later stages. This number system is signed digit number representation. This RBSD multiplier is implemented using VIVADO 2019.2 version. The multiplier is implemented in VHDL language. Although there is a slight increase in the delay using VIVADO Multiplier, there is a significant decrease in the number of LUT used. We have used artix FPGA[4] with part number xc7a200tisbv484.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

A Carry-Free Multiplication Implementation Method

Delay caused by carry propagation is an unfavourable issue that much affects the efficiency of numerical computing in computer system. And the more data bits of the operands, the worse the delay. As data bits of the operands in optical computer can be huge because of the high information capability of light, this makes carry delay be very serious. As multiplication is one of the most important and popular calculations and many multiplications can be carried out in parallel by utilizing huge number of data bits of optical computer, study on how to reduce or even mitigate carry delay in multiplication is very important. To improve the multiplication efficiency, a new carry free method to design and implement multiplication based on Ternary Optical Computer (TOC) is put forward. Fully considering the relations between the operands based on modified signed-digit (MSD) number system, a parallel mulitplication implemeation strategy together with its resource allocation method is presented. The experimental results show that the proposed strategy is correct. It exerts the advantages of optical computing and ensures that no carry delay is introduced in the process of multiplication which much improves the efficiency of optical multiplication applications.

Carry-free full-symbol one-step modified signed-digit addition.

Optical computing has advantages over electronic computing because it can carry much more information and process more data bits. Providing that carry-look-ahead is applied in optical computing in the same way electronic computing accomplishes addition calculation, it will be more inefficient because of the delay caused by a large number of serial carries. On the basis of the research on relations among the augend, addend, results, and the redundancy of modified signed-digit (MSD) number, the implementation method of carry-free one-step MSD addition is presented. Meanwhile, the corresponding logical light path scheme is designed in this paper. Extensive experimental results show that the proposed implementation method of one-step addition is correct, and the designed light path scheme is reasonable.

An optical implementation method for symmetric MSD number

Symmetric modified signed-digit (MSD) number is much advantageous over other numbers. It can implement optical addition operation in one step without carry delay which will much affect the efficiency of numerical operation in computer system. However, study on how to obtain symmetric MSD (SMSD) number has been little concerned. Based on the mapping relations between common MSD number and SMSD number, conversion rules are presented. Following the rules, the optical paths of the converters to implement the conversion are designed. Combining the converters, the optical path of the general converter that can be used to implement the conversion from common MSD number to SMSD number is presented. Simulation results show that the method and the optical path of the converter are correct. They can be used to effectively convert MSD number into the corresponding SMSD number.

Efficient signed-digit-to-canonical-signed-digit recoding circuits

In this study, we propose a new signed-digit-to-canonical-signed-digit recoding circuit based on parallel prefix structures. Several articles have been devoted to the study of canonical signed-digit recoding circuits. However, most of those re-code from 2's complement binary number representation. Unlike those, our proposed architectures convert from signed-digit number representation. The circuit structure is somewhat different from those in previous articles, because each digit in the input is accompanied by its sign. We evaluate the proposed circuit and compare it with a circuit based on the conditional sum structure. We show that the proposed architectures performs faster by 30% or more than the circuit based on the conditional sum structure.

Reverse Conversion Schemes for Signed-Digit Number Systems: A Survey

Although signed-digit number systems have received a considerable attention, the transformation of signed-digit numbers back into the conventional forms, known as reverse conversion, is still a performance bottleneck of signed-digit arithmetic. In this paper, a literature survey of reverse conversion schemes for signed-digit number systems is performed on the basis of the articles published from recognized platforms for the past few decades. The survey reveals some specific problems of this field, which need further investigations.

Fast Computation Using High Radix Signed Digit Number with Different Adders

Fast Computation Using High Radix Signed Digit Number with Different Adders

Design of a high-efficient MSD adder

Carry propagation delay is a big obstacle to improve the addition efficiency in computer system. And the more data bits the operands have, the delay is more serious. As data bits of operand in optical computer can be huge this makes carry delay be very serious. How to decrease or even mitigate carry delay in addition is very important to promote optical computer in numerical computing applications. To improve the addition efficiency, a new method to design and implement optical adder is put forward. Fully considering the relations between the addend and augend based on modified signed-digit (MSD) number system operands, division algorithm is presented. It makes the design and implementation of the adder much easy and feasible. Besides, it also guarantees that no carry delay is introduced in the process of addition. Meanwhile, the architecture of the adder, its implementation as well as the auxiliary electronic circuit are also presented. Experimental results show that the architecture and design of the new MSD adder are correct. It can avoid carry propagation and is much efficient for optical addition operation.

Notes on &quotA Novel Conversion Scheme from a Redundant Binary Number to Two's Complement Binary Number for Parallel Architectures&quot proposed by Choo et. al.

In this article, it is shown that although the reverse conversion scheme for binary signed-digit number system proposed by Choo et. al. can not support full parallelism; the rules on which it is based are correct. In this connection, a mathematical induction technique is used to validate the decomposition rules. Accordingly, it can be inferred that the reverse conversion scheme for binary signed-digit number system proposed by Veeramachaneni et. al. works correctly and performs reverse conversion in Ω (log n) time, where, n is the input size. As a consequence, the scheme by Veeramachaneni et. al. need to be considered as a potential contender of the more recent schemes for the same. General Terms Unconventional Number System, Computer Arithmetic Algorithm.

Principle and design of ternary optical accumulator implementing M-k-B addition

In this paper, we focus on the M-k-B addition of the form M þ B1 þ B2 þ :::þ Bk based on an optical approach, where M is a modified signed-digit number and Bi's are the binary numbers. We present three trans- forms C, P, and R and an algorithm of carry-free parallel addition of M and B. Based on these transforms, the accumulation computing M-k-B is proposed which indicates that it requires only 2k steps to complete the addition in parallel. Then, the optical structures for C, P, and R transforms as well as the adder realizing M þ B are designed. Moreover, a photoelectric implementation of the ternary optical adder to realize M-1-B structure using the reconfiguration method is presented. Additionally, an optical experiment for 2-bit M-2-B ternary adder is carried out to demonstrate the feasibility of M-k-B adder. The work indicates that the parallel carry-free addition in form M0 þ B1 þ B2 þ :::þ Bk is easily completed. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI. (DOI: 10.1117/1.OE.53.9.095108)

All-optical polarization-encoded negabinary signed-digit adder designs using terahertz-optical-asymmetric-demultiplexer switches

Incontrast to intensity-encoded negabinary modified signed-digit number representation, a polarization-encoding scheme is proposed to design all-optical adders. The utilization of the proposed polarization-encoding produces more efficient circuits in terms of gates numbers and circuit delays. Three all-optical adder circuits are designed using Terahertz-Optical-Asymmetric-Demultiplexer (TOAD) switches,polarization beam splitters, polarization converters, and beam combiners. Itwill be shown that the proposed circuits utilize 51.7%, 45.5%, and 21% less gates and they are faster by 44.4%, 42.9%, and 40%, respectively, than thecorresponding intensity-encoded circuits.

Comments on &quotArea Time Efficient Sign Detection Technique for Binary Signed-Digit Number System&quot proposed by Srikanthan, Lam and Suman

It is shown that the sign detection technique for binary signeddigit number system reported by Srikanthan, Lam and Suman [1] cannot work correctly. The root cause of the problem is detected and some modifications are proposed. The proposed modifications are found to be significant. General Terms Unconventional Number Systems, Algorithm, VLSI