Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA

Abstract

Abstract Now a day’s speed is very important to meet the requirement of user in today’s chips. We want faster smart phones, laptops and other gadgets that can work at a speed even beyond our imagination. In this paper we have designed a fast multiplier which can provide better results. RBSD stands for Redundant Binary Signed Digit number system which enables fast computing by reducing carry propagation time as carry is not propagated to later stages. This number system is signed digit number representation. This RBSD multiplier is implemented using VIVADO 2019.2 version. The multiplier is implemented in VHDL language. Although there is a slight increase in the delay using VIVADO Multiplier, there is a significant decrease in the number of LUT used. We have used artix FPGA[4] with part number xc7a200tisbv484.